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stm32g0: fix bad typos in memorymap, impacting tim1 and tim15-17.

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This commit is contained in:
Guillaume Revaillot 2019-08-27 16:23:54 +02:00
parent 7ff54cb7f0
commit ec597796d7
1 changed files with 4 additions and 4 deletions
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8
include/libopencm3/stm32/g0/memorymap.h
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@ -58,12 +58,12 @@
#define SYSCFG_ITLINE_BASE (PERIPH_BASE_APB2 + 0x0080)
#define COMP_BASE (PERIPH_BASE_APB2 + 0x0200)
#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400)
#define TIM1_BASE (PERIPH_BASE_APB1 + 0x2C00)
#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00)
#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
#define TIM15_BASE (PERIPH_BASE_APB1 + 0x4000)
#define TIM16_BASE (PERIPH_BASE_APB1 + 0x4400)
#define TIM17_BASE (PERIPH_BASE_APB1 + 0x4800)
#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000)
#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400)
#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800)
#define DBGMCU_BASE (PERIPH_BASE_APB2 + 0x5800)
/* AHB */