diff --git a/include/libopencm3/cm3/fpb.h b/include/libopencm3/cm3/fpb.h
index 3c1d22b7..fe624da5 100644
--- a/include/libopencm3/cm3/fpb.h
+++ b/include/libopencm3/cm3/fpb.h
@@ -40,6 +40,12 @@
 /* Flash Patch Comparator (FPB_COMPx) */
 #define FPB_COMP			(&MMIO32(FPB_BASE + 8))
 
+/* CoreSight Lock Status Register for this peripheral */
+#define FPB_LSR				MMIO32(FPB_BASE + 0xFB4)
+/* CoreSight Lock Access Register for this peripheral */
+#define FPB_LAR				MMIO32(FPB_BASE + 0xFB0)
+
+
 /* TODO: PID, CID */
 
 /* --- FPB_CTRL values ----------------------------------------------------- */
diff --git a/include/libopencm3/cm3/itm.h b/include/libopencm3/cm3/itm.h
index 3d907ed8..8b55119c 100644
--- a/include/libopencm3/cm3/itm.h
+++ b/include/libopencm3/cm3/itm.h
@@ -29,8 +29,10 @@
 
 /* --- ITM registers ------------------------------------------------------- */
 
-/* Stimulus Port x (ITM_STIM[x]) */
-#define ITM_STIM			(&MMIO32(ITM_BASE))
+/* Stimulus Port x (ITM_STIM<sz>(x)) */
+#define ITM_STIM8(n)			(MMIO8(ITM_BASE + (n*4)))
+#define ITM_STIM16(n)			(MMIO16(ITM_BASE + (n*4)))
+#define ITM_STIM32(n)			(MMIO32(ITM_BASE + (n*4)))
 
 /* Trace Enable ports (ITM_TER[x]) */
 #define ITM_TER				(&MMIO32(ITM_BASE + 0xE00))
@@ -41,6 +43,11 @@
 /* Trace Control (ITM_TCR) */
 #define ITM_TCR				MMIO32(ITM_BASE + 0xE80)
 
+/* CoreSight Lock Status Register for this peripheral */
+#define ITM_LSR			MMIO32(ITM_BASE + 0xFB4)
+/* CoreSight Lock Access Register for this peripheral */
+#define ITM_LAR			MMIO32(ITM_BASE + 0xFB0)
+
 /* TODO: PID, CID */
 
 /* --- ITM_STIM values ----------------------------------------------------- */
diff --git a/include/libopencm3/cm3/memorymap.h b/include/libopencm3/cm3/memorymap.h
index 7339fdbf..450eb586 100644
--- a/include/libopencm3/cm3/memorymap.h
+++ b/include/libopencm3/cm3/memorymap.h
@@ -48,15 +48,6 @@
 #define TPIU_BASE                       (PPBI_BASE + 0x40000)
 #endif
 
-/* --- ITM: Instrumentation Trace Macrocell --- */
-/* TODO */
-
-/* --- DWT: Data Watchpoint and Trace unit --- */
-/* TODO */
-
-/* --- FPB: Flash Patch and Breakpoint unit --- */
-/* TODO */
-
 /* --- SCS: System Control Space --- */
 
 /* Those defined only on ARMv7 and above */
diff --git a/include/libopencm3/cm3/scs.h b/include/libopencm3/cm3/scs.h
index c0787170..7bf98601 100644
--- a/include/libopencm3/cm3/scs.h
+++ b/include/libopencm3/cm3/scs.h
@@ -308,6 +308,11 @@
 /* DWT_PCSR register */
 #define SCS_DWT_PCSR		MMIO32(DWT_BASE + 0x18)
 
+/* CoreSight Lock Status Register for this peripheral */
+#define SCS_DWT_LSR		MMIO32(SCS_DWT_BASE + 0xFB4)
+/* CoreSight Lock Access Register for this peripheral */
+#define SCS_DWT_LAR		MMIO32(SCS_DWT_BASE + 0xFB0)
+
 /* --- SCS_DWT_CTRL values ------------------------------------------------- */
 /*
  * Enables CYCCNT:
@@ -316,6 +321,13 @@
  */
 #define SCS_DWT_CTRL_CYCCNTENA	(BIT0)
 
+/* CoreSight Lock Status Register lock status bit */
+#define SCS_LSR_SLK		(1<<1)
+/* CoreSight Lock Status Register lock availability bit */
+#define SCS_LSR_SLI		(1<<0)
+/* CoreSight Lock Access key, common for all */
+#define SCS_LAR_KEY		0xC5ACCE55
+
 /* TODO bit definition values for other DWT_XXX register */
 
 /* Macro to be called at startup to enable SCS & Cycle Counter */
diff --git a/include/libopencm3/cm3/tpiu.h b/include/libopencm3/cm3/tpiu.h
index d14cc02b..ff215116 100644
--- a/include/libopencm3/cm3/tpiu.h
+++ b/include/libopencm3/cm3/tpiu.h
@@ -50,25 +50,13 @@
 /* (TPIU_DEVID) */
 #define TPIU_DEVID			MMIO32(TPIU_BASE + 0xFC8)
 
+/* CoreSight Lock Status Register for this peripheral */
+#define TPIU_LSR			MMIO32(TPIU_BASE + 0xFB4)
+/* CoreSight Lock Access Register for this peripheral */
+#define TPIU_LAR			MMIO32(TPIU_BASE + 0xFB0)
+
 /* TODO: PID, CID */
 
-/* --- TPIU_SSPSR values --------------------------------------------------- */
-
-/*
- * bit[N] == 0, trace port width of (N+1) not supported
- * bit[N] == 1, trace port width of (N+1) supported
- */
-#define TPIU_SSPSR_BYTE			(1 << 0)
-#define TPIU_SSPSR_HALFWORD		(1 << 1)
-#define TPIU_SSPSR_WORD			(1 << 3)
-
-/* --- TPIU_SSPSR values --------------------------------------------------- */
-
-/* Same format as TPIU_SSPSR, except only one is set */
-#define TPIU_CSPSR_BYTE			(1 << 0)
-#define TPIU_CSPSR_HALFWORD		(1 << 1)
-#define TPIU_CSPSR_WORD			(1 << 3)
-
 /* --- TPIU_ACPR values ---------------------------------------------------- */
 
 /* Bits 31:16 - Reserved */