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stm32: pwr-v1: doxygen-ize bit definitions.

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Rich commentary already existed, just add the second * to let doxygen
pick it up.
This commit is contained in:
Karl Palsson 2017-12-07 10:30:11 +00:00
parent 297d996fa0
commit ef04708e92
1 changed files with 12 additions and 12 deletions
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24
include/libopencm3/stm32/common/pwr_common_v1.h
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@ -37,17 +37,17 @@ specific memorymap.h header before including this header file.*/
/* --- PWR registers ------------------------------------------------------- */ /* --- PWR registers ------------------------------------------------------- */
/* Power control register (PWR_CR) */ /** Power control register (PWR_CR) */
#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) #define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
/* Power control/status register (PWR_CSR) */ /** Power control/status register (PWR_CSR) */
#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) #define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
/* --- PWR_CR values ------------------------------------------------------- */ /* --- PWR_CR values ------------------------------------------------------- */
/* Bits [31:9]: Reserved, must be kept at reset value. */ /* Bits [31:9]: Reserved, must be kept at reset value. */
/* DBP: Disable backup domain write protection */ /** DBP: Disable backup domain write protection */
#define PWR_CR_DBP (1 << 8) #define PWR_CR_DBP (1 << 8)
/* PLS[7:5]: PVD level selection */ /* PLS[7:5]: PVD level selection */
@ -67,37 +67,37 @@ specific memorymap.h header before including this header file.*/
/**@}*/ /**@}*/
#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB) #define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
/* PVDE: Power voltage detector enable */ /** PVDE: Power voltage detector enable */
#define PWR_CR_PVDE (1 << 4) #define PWR_CR_PVDE (1 << 4)
/* CSBF: Clear standby flag */ /** CSBF: Clear standby flag */
#define PWR_CR_CSBF (1 << 3) #define PWR_CR_CSBF (1 << 3)
/* CWUF: Clear wakeup flag */ /** CWUF: Clear wakeup flag */
#define PWR_CR_CWUF (1 << 2) #define PWR_CR_CWUF (1 << 2)
/* PDDS: Power down deepsleep */ /** PDDS: Power down deepsleep */
#define PWR_CR_PDDS (1 << 1) #define PWR_CR_PDDS (1 << 1)
/* LPDS: Low-power deepsleep */ /** LPDS: Low-power deepsleep */
#define PWR_CR_LPDS (1 << 0) #define PWR_CR_LPDS (1 << 0)
/* --- PWR_CSR values ------------------------------------------------------ */ /* --- PWR_CSR values ------------------------------------------------------ */
/* Bits [31:9]: Reserved, must be kept at reset value. */ /* Bits [31:9]: Reserved, must be kept at reset value. */
/* EWUP: Enable WKUP pin */ /** EWUP: Enable WKUP pin */
#define PWR_CSR_EWUP (1 << 8) #define PWR_CSR_EWUP (1 << 8)
/* Bits [7:3]: Reserved, must be kept at reset value. */ /* Bits [7:3]: Reserved, must be kept at reset value. */
/* PVDO: PVD output */ /** PVDO: PVD output */
#define PWR_CSR_PVDO (1 << 2) #define PWR_CSR_PVDO (1 << 2)
/* SBF: Standby flag */ /** SBF: Standby flag */
#define PWR_CSR_SBF (1 << 1) #define PWR_CSR_SBF (1 << 1)
/* WUF: Wakeup flag */ /** WUF: Wakeup flag */
#define PWR_CSR_WUF (1 << 0) #define PWR_CSR_WUF (1 << 0)
/* --- PWR function prototypes ------------------------------------------- */ /* --- PWR function prototypes ------------------------------------------- */