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stm32/f0: minor cleanup of HSI clock functions

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- add brief descriptions for HSI clock functions
- use rcc_set_pll_source to set PLL source in RCC_CFGR

Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
This commit is contained in:
Sergey Matyukevich 2016-12-17 22:14:16 +03:00 committed by Karl Palsson
parent 1b97ecefff
commit ef668edef6
1 changed files with 39 additions and 10 deletions
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49
lib/stm32/f0/rcc.c
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@ -591,6 +591,11 @@ enum rcc_osc rcc_usb_clock_source(void)
return (RCC_CFGR3 & RCC_CFGR3_USBSW) ? RCC_PLL : RCC_HSI48; return (RCC_CFGR3 & RCC_CFGR3_USBSW) ? RCC_PLL : RCC_HSI48;
} }
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock HSI at 8MHz
*/
void rcc_clock_setup_in_hsi_out_8mhz(void) void rcc_clock_setup_in_hsi_out_8mhz(void)
{ {
rcc_osc_on(RCC_HSI); rcc_osc_on(RCC_HSI);
@ -606,6 +611,11 @@ void rcc_clock_setup_in_hsi_out_8mhz(void)
rcc_ahb_frequency = 8000000; rcc_ahb_frequency = 8000000;
} }
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 16MHz from HSI
*/
void rcc_clock_setup_in_hsi_out_16mhz(void) void rcc_clock_setup_in_hsi_out_16mhz(void)
{ {
rcc_osc_on(RCC_HSI); rcc_osc_on(RCC_HSI);
@ -619,8 +629,7 @@ void rcc_clock_setup_in_hsi_out_16mhz(void)
/* 8MHz * 4 / 2 = 16MHz */ /* 8MHz * 4 / 2 = 16MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL4); rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL4);
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
RCC_CFGR &= ~RCC_CFGR_PLLSRC;
rcc_osc_on(RCC_PLL); rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL);
@ -630,6 +639,10 @@ void rcc_clock_setup_in_hsi_out_16mhz(void)
rcc_ahb_frequency = 16000000; rcc_ahb_frequency = 16000000;
} }
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 24MHz from HSI
*/
void rcc_clock_setup_in_hsi_out_24mhz(void) void rcc_clock_setup_in_hsi_out_24mhz(void)
{ {
@ -644,8 +657,7 @@ void rcc_clock_setup_in_hsi_out_24mhz(void)
/* 8MHz * 6 / 2 = 24MHz */ /* 8MHz * 6 / 2 = 24MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL6); rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL6);
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
RCC_CFGR &= ~RCC_CFGR_PLLSRC;
rcc_osc_on(RCC_PLL); rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL);
@ -655,6 +667,11 @@ void rcc_clock_setup_in_hsi_out_24mhz(void)
rcc_ahb_frequency = 24000000; rcc_ahb_frequency = 24000000;
} }
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 32MHz from HSI
*/
void rcc_clock_setup_in_hsi_out_32mhz(void) void rcc_clock_setup_in_hsi_out_32mhz(void)
{ {
rcc_osc_on(RCC_HSI); rcc_osc_on(RCC_HSI);
@ -668,8 +685,7 @@ void rcc_clock_setup_in_hsi_out_32mhz(void)
/* 8MHz * 8 / 2 = 32MHz */ /* 8MHz * 8 / 2 = 32MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL8); rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL8);
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
RCC_CFGR &= ~RCC_CFGR_PLLSRC;
rcc_osc_on(RCC_PLL); rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL);
@ -679,6 +695,11 @@ void rcc_clock_setup_in_hsi_out_32mhz(void)
rcc_ahb_frequency = 32000000; rcc_ahb_frequency = 32000000;
} }
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 40MHz from HSI
*/
void rcc_clock_setup_in_hsi_out_40mhz(void) void rcc_clock_setup_in_hsi_out_40mhz(void)
{ {
rcc_osc_on(RCC_HSI); rcc_osc_on(RCC_HSI);
@ -692,8 +713,7 @@ void rcc_clock_setup_in_hsi_out_40mhz(void)
/* 8MHz * 10 / 2 = 40MHz */ /* 8MHz * 10 / 2 = 40MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL10); rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL10);
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
RCC_CFGR &= ~RCC_CFGR_PLLSRC;
rcc_osc_on(RCC_PLL); rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL);
@ -703,6 +723,11 @@ void rcc_clock_setup_in_hsi_out_40mhz(void)
rcc_ahb_frequency = 40000000; rcc_ahb_frequency = 40000000;
} }
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 48MHz from HSI
*/
void rcc_clock_setup_in_hsi_out_48mhz(void) void rcc_clock_setup_in_hsi_out_48mhz(void)
{ {
rcc_osc_on(RCC_HSI); rcc_osc_on(RCC_HSI);
@ -716,8 +741,7 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
/* 8MHz * 12 / 2 = 48MHz */ /* 8MHz * 12 / 2 = 48MHz */
rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL12); rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL12);
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
RCC_CFGR &= ~RCC_CFGR_PLLSRC;
rcc_osc_on(RCC_PLL); rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL);
@ -727,6 +751,11 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
rcc_ahb_frequency = 48000000; rcc_ahb_frequency = 48000000;
} }
/*---------------------------------------------------------------------------*/
/** @brief RCC Set System Clock HSI48 at 48MHz
*/
void rcc_clock_setup_in_hsi48_out_48mhz(void) void rcc_clock_setup_in_hsi48_out_48mhz(void)
{ {
rcc_osc_on(RCC_HSI48); rcc_osc_on(RCC_HSI48);