SWM050: Adds the timer peripheral and updates the README.
This commit is contained in:
Caleb Szalacinski
Karl Palsson
parent
7daa6f15bf
commit
f06a1ca958
@ -18,6 +18,7 @@ Currently (at least partly) supported microcontrollers:
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- EFM32 Gecko series (only core support)
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- Freescale Vybrid VF6xx
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- Qorvo (formerly ActiveSemi) PAC55XX
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- Synwit SWM050
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The library is written completely from scratch based on the vendor datasheets,
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programming manuals, and application notes. The code is meant to be used
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233
include/libopencm3/swm050/timer.h
Normal file
233
include/libopencm3/swm050/timer.h
Normal file
@ -0,0 +1,233 @@
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/** @defgroup timer_defines Timer Defines
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*
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* @brief <b>Defined Constants and Types for the SWM050 Timer</b>
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*
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* @ingroup SWM050_defines
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2020 Caleb Szalacinski <contact@skiboy.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_TIMER_H
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#define LIBOPENCM3_TIMER_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/swm050/memorymap.h>
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/* Timer select */
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/** @defgroup timer_select Timer Select
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@{*/
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#define TIMER_SE0 TIMER_SE0_BASE
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#define TIMER_SE1 TIMER_SE1_BASE
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/*@}*/
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/* Timer level definitions */
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/** @defgroup timer_level Timer Level
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@{*/
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enum timer_level {
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TIMER_LEVEL_LOW,
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TIMER_LEVEL_HIGH
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};
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/*@}*/
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/* Timer edge mode definitions */
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/** @defgroup timer_edge_modes Timer Edge Modes
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@{*/
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enum timer_edge_modes {
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/* Trigger on rising edge */
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TIMER_EDGE_RISING,
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/* Trigger on falling edge */
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TIMER_EDGE_FALLING
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};
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/*@}*/
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/* Timer operation mode definitions */
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/** @defgroup timer_operation_modes Timer Operation Modes
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@{*/
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enum timer_operation_modes {
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TIMER_MODE_COUNTER,
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TIMER_MODE_PWM,
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TIMER_MODE_PULSE_CAPTURE,
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TIMER_MODE_DUTY_CYCLE_CAPTURE
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};
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/*@}*/
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/* Timer clock source definitions */
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/** @defgroup timer_clk_src Timer Clock Source
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@{*/
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enum timer_clk_src {
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TIMER_CLK_INTERNAL,
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TIMER_CLK_EXTERNAL
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};
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/*@}*/
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/* Timer interrupt mask definitions */
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/** @defgroup timer_int_masked Timer Interrupt Mask
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@{*/
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enum timer_int_masked {
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TIMER_UNMASKED,
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TIMER_MASKED
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};
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/*@}*/
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/* Timer loop mode definitions */
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/** @defgroup timer_loop_modes Timer Loop Modes
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@{*/
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enum timer_loop_modes {
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TIMER_LOOP_MODE,
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TIMER_SINGLE_MODE
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};
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/*@}*/
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/* Timer output mode definitions */
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/** @defgroup timer_output_modes Timer Output Modes
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@{*/
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enum timer_output_modes {
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TIMER_OUTPUT_NONE,
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TIMER_OUTPUT_INVERT,
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TIMER_OUTPUT_HIGH,
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TIMER_OUTPUT_LOW
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};
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/*@}*/
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/* Timer PWM period definitions */
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/** @defgroup timer_pwm_period Timer PWM Periods
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@{*/
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enum timer_pwm_period {
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TIMER_PERIOD_0,
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TIMER_PERIOD_1
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};
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/*@}*/
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/* Timer clock divider mask */
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/** @defgroup timer_div_mask Timer Clock Divider Mask
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@{*/
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#define TIMER_DIV_MASK (0x3F << 16)
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/*@}*/
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/* Timer operation mode mask */
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/** @defgroup timer_operation_mask Timer Operation Mode Mask
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@{*/
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#define TIMER_OPER_MODE_MASK (0x3 << 4)
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/*@}*/
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/* Timer output mode mask */
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/** @defgroup timer_output_mask Timer Output Mode Mask
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@{*/
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#define TIMER_OUTP_MODE_MASK (0x3 << 12)
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/*@}*/
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/* Timer subregisters */
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/** @defgroup timer_subregisters Timer Subregisters
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@{*/
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#define TIMER_CTRL_EN 1
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/** Clock source selection */
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#define TIMER_CTRL_OSCMOD (1 << 8)
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/** Valid edge selection */
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#define TIMER_CTRL_TMOD (1 << 16)
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/** Loop mode selection */
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#define TIMER_CTRL_LMOD (1 << 28)
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/** Interrupt mask */
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#define TIMER_INTCTL_INTMSK (1 << 1)
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/** Interrupt enable */
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#define TIMER_INTCTL_INTEN 1
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/*@}*/
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/* Timer registers */
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/** @defgroup timer_registers Timer Registers
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@{*/
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/** Timer control register */
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#define TIMER_CTRL(x) MMIO32(x + 0x0)
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/** The target value(s). Treated as uint32_t in counter mode (0), and as 2
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uint16_t values in PWM mode (1) */
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#define TIMER_TARVAL(x) MMIO32(x + 0x4)
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/** Current count value in modes 0, 2, and 3 */
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#define TIMER_CURVAL(x) MMIO32(x + 0x8)
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/** Cycle width in mode 3 */
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#define TIMER_CAPW(x) MMIO32(x + 0xC)
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/** Pulse width in modes 2 and 3 */
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#define TIMER_CAPLH(x) MMIO32(x + 0x10)
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/** PWM state in mode 1 */
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#define TIMER_MOD2LF(x) MMIO32(x + 0x14)
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/** Timer output pin value */
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#define TIMER_OUTPVAL(x) MMIO32(x + 0x80)
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/** Interrupt enable and mask */
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#define TIMER_INTCTL(x) MMIO32(x + 0x84)
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/** Interrupt status before masking */
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#define TIMER_INTSTAT(x) MMIO32(x + 0x88)
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/** Interrupt status after masking */
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#define TIMER_INTMSKSTAT(x) MMIO32(x + 0x8C)
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/** Interrupt overflow; 1 if interrupt occurs again without being cleared */
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#define TIMER_INTFLAG(x) MMIO32(x + 0x90)
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/*@}*/
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BEGIN_DECLS
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void timer_counter_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_loop_modes loop_mode,
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enum timer_clk_src clk_src,
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enum timer_output_modes output_mode,
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enum timer_level output_level,
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uint32_t target);
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void timer_pwm_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_clk_src clk_src,
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enum timer_level output_level,
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uint16_t target1,
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uint16_t target2);
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void timer_pulse_capture_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_loop_modes loop_mode);
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void timer_duty_cycle_capture_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_loop_modes loop_mode);
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void timer_clock_div(uint8_t div);
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void timer_enable(uint32_t timer, bool en);
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void timer_clock_enable(uint32_t timer, bool en);
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void timer_operation_mode(uint32_t timer, enum timer_operation_modes mode);
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void timer_output_mode(uint32_t timer, enum timer_output_modes mode);
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void timer_output_level(uint32_t timer, enum timer_level level);
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void timer_edge_mode(uint32_t timer, enum timer_edge_modes mode);
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void timer_loop_mode(uint32_t timer, enum timer_loop_modes mode);
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void timer_clock_source(uint32_t timer, enum timer_clk_src src);
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void timer_counter_target_value(uint32_t timer, uint32_t target);
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void timer_pwm_target_value(uint32_t timer, uint16_t period0, uint16_t period1);
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void timer_int_enable(uint32_t timer, bool en);
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void timer_int_mask(uint32_t timer, enum timer_int_masked masked);
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uint32_t timer_get_current_value(uint32_t timer);
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uint32_t timer_get_cycle_width(uint32_t timer);
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uint32_t timer_get_pulse_width(uint32_t timer);
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enum timer_pwm_period timer_get_pwm_period(uint32_t timer);
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bool timer_int_status(uint32_t timer);
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bool timer_int_raw_status(uint32_t timer);
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bool timer_int_overflow_status(uint32_t timer);
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END_DECLS
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#endif
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/**@}*/
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@ -38,6 +38,7 @@ OBJS += flash.o
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OBJS += gpio.o
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OBJS += pwr.o
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OBJS += syscon.o
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OBJS += timer.o
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OBJS += wdt.o
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VPATH += ../cm3
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455
lib/swm050/timer.c
Normal file
455
lib/swm050/timer.c
Normal file
@ -0,0 +1,455 @@
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/** @defgroup timer_file Timer peripheral API
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* @brief SWM050 Timer API.
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* @ingroup peripheral_apis
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* LGPL License Terms @ref lgpl_license
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* @author @htmlonly © @endhtmlonly 2020
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* Caleb Szalacinski <contact@skiboy.net>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2020 Caleb Szalacinski <contact@skiboy.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/swm050/timer.h>
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#include <libopencm3/swm050/sysctl.h>
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#include <libopencm3/swm050/syscon.h>
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/**
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* Internal function for timer setup.
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* @param timer Select timer @ref timer_select
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* @param timer_int_en Passed to @ref timer_int_enable()
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* @param op_mode Passed to @ref timer_operation_mode()
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* @param edge_mode Passed to @ref timer_edge_mode()
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* @param loop_mode Passed to @ref timer_loop_mode()
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* @param clk_src Passed to @ref timer_clock_source()
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* @param output_mode Passed to @ref timer_output_mode()
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* @param output_level Passed to @ref timer_output_level()
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*/
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static void timer_setup_internal(uint32_t timer,
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bool timer_int_en,
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enum timer_operation_modes op_mode,
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enum timer_edge_modes edge_mode,
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enum timer_loop_modes loop_mode,
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enum timer_clk_src clk_src,
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enum timer_output_modes output_mode,
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enum timer_level output_level)
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{
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timer_enable(timer, false);
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/* Conserve power by shutting off the unneeded clock */
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timer_clock_enable(timer, (clk_src == TIMER_CLK_INTERNAL));
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timer_loop_mode(timer, loop_mode);
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timer_output_mode(timer, output_mode);
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timer_output_level(timer, output_level);
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timer_clock_source(timer, clk_src);
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timer_operation_mode(timer, op_mode);
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timer_edge_mode(timer, edge_mode);
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timer_int_enable(timer, timer_int_en);
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timer_int_mask(timer, TIMER_UNMASKED);
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}
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/**
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* Setup the timer in counter mode.
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* @note Call @ref timer_enable() when you are ready to start the timer.
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* @note Be sure to set the alternate functions of the timer pins
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* with @ref syscon_sel_af() and disable SWD on those pins
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* with @ref syscon_sel_swd() as needed.
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* @note If interrupts are enabled here, the interrupt should also be enabled
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* using the NVIC before enabling the timer.
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* @param timer Select timer @ref timer_select
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* @param timer_int_en Passed to @ref timer_int_enable()
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* @param edge_mode Passed to @ref timer_edge_mode()
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* @param loop_mode Passed to @ref timer_loop_mode()
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* @param clk_src Passed to @ref timer_clock_source()
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* @param output_mode Passed to @ref timer_output_mode()
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* @param output_level Passed to @ref timer_output_level()
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*/
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void timer_counter_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_loop_modes loop_mode,
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enum timer_clk_src clk_src,
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enum timer_output_modes output_mode,
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enum timer_level output_level,
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uint32_t target)
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{
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timer_setup_internal(timer, timer_int_en, TIMER_MODE_COUNTER, edge_mode,
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loop_mode, clk_src, output_mode, output_level);
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timer_counter_target_value(timer, target);
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}
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/**
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* Setup the timer in PWM mode.
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* @note Call @ref timer_enable() when you are ready to start the timer.
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* @note Be sure to set the alternate functions of the timer pins
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* with @ref syscon_sel_af() and disable SWD on those pins
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* with @ref syscon_sel_swd() as needed.
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* @note If interrupts are enabled here, the interrupt should also be enabled
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* using the NVIC before enabling the timer.
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* @param timer Select timer @ref timer_select
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* @param timer_int_en Passed to @ref timer_int_enable()
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* @param edge_mode Passed to @ref timer_edge_mode()
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* @param loop_mode Passed to @ref timer_loop_mode()
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* @param clk_src Passed to @ref timer_clock_source()
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* @param output_mode Passed to @ref timer_output_mode()
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* @param output_level Passed to @ref timer_output_level()
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* @param period0 Passed to @ref timer_pwm_target_value()
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* @param period1 Passed to @ref timer_pwm_target_value()
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*/
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void timer_pwm_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_clk_src clk_src,
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enum timer_level output_level,
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uint16_t period0,
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uint16_t period1)
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{
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timer_setup_internal(timer, timer_int_en, TIMER_MODE_PWM, edge_mode,
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TIMER_LOOP_MODE, clk_src, TIMER_OUTPUT_NONE,
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output_level);
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timer_pwm_target_value(timer, period0, period1);
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}
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/**
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* Setup the timer in pulse capture mode.
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* @note Call @ref timer_enable() when you are ready to start the timer.
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* @note Be sure to set the alternate functions of the timer pins
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* with @ref syscon_sel_af() and disable SWD on those pins
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* with @ref syscon_sel_swd() as needed.
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* @note If interrupts are enabled here, the interrupt should also be enabled
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* using the NVIC before enabling the timer.
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* @param timer Select timer @ref timer_select
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* @param timer_int_en Passed to @ref timer_int_enable()
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* @param edge_mode Passed to @ref timer_edge_mode()
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* @param loop_mode Passed to @ref timer_loop_mode()
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*/
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void timer_pulse_capture_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_loop_modes loop_mode)
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{
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timer_setup_internal(timer, timer_int_en, TIMER_MODE_PULSE_CAPTURE,
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edge_mode, loop_mode, TIMER_CLK_INTERNAL,
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TIMER_OUTPUT_NONE, TIMER_LEVEL_LOW);
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}
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/**
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* Setup the timer in duty cycle capture mode.
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* @note Call @ref timer_enable() when you are ready to start the timer.
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* @note Be sure to set the alternate functions of the timer pins
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* with @ref syscon_sel_af() and disable SWD on those pins
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* with @ref syscon_sel_swd() as needed.
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* @note If interrupts are enabled here, the interrupt should also be enabled
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* using the NVIC before enabling the timer.
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* @param timer Select timer @ref timer_select
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* @param timer_int_en Passed to @ref timer_int_enable()
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* @param edge_mode Passed to @ref timer_edge_mode()
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* @param loop_mode Passed to @ref timer_loop_mode()
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*/
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void timer_duty_cycle_capture_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_loop_modes loop_mode)
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{
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timer_setup_internal(timer, timer_int_en, TIMER_MODE_DUTY_CYCLE_CAPTURE,
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edge_mode, loop_mode, TIMER_CLK_INTERNAL,
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TIMER_OUTPUT_NONE, TIMER_LEVEL_LOW);
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}
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/**
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* Set the timer clock divider, based off of the 18MHz oscillator
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* @param div Timer clock divider. Only the 6 least-significant bits are used,
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* Takes values from 0 to 63 (in reality the possible values are the even
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* numbers from 2 to 62, as well as the number 1). Anything after the 6
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* least-significant bits are stripped off of the value. If the value is 0,
|
||||
* it will be treated as a 1. All odd values other than 1 are rounded down
|
||||
* to the closest even value, due to the fact that all odd values are
|
||||
* treated by the register as a 1, which would likely be unexpected. A
|
||||
* value of 0 would also normally be treated as a 2, which would also be
|
||||
* unexpected behavior.
|
||||
*/
|
||||
void timer_clock_div(uint8_t div)
|
||||
{
|
||||
/* If the value is 0 or 1, make it odd, meaning no divide. */
|
||||
/* Otherwise, drop div to the closest even value. */
|
||||
div = (div <= 1) ? 1 : (div & ~0x1);
|
||||
SYSCTL_SYS_CFG_1 = (~TIMER_DIV_MASK & SYSCTL_SYS_CFG_1) | (div << 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* Enables or disables the timer.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param en Enable or disable the timer
|
||||
*/
|
||||
void timer_enable(uint32_t timer, bool en)
|
||||
{
|
||||
if (en) {
|
||||
TIMER_CTRL(timer) |= TIMER_CTRL_EN;
|
||||
} else {
|
||||
TIMER_CTRL(timer) &= ~TIMER_CTRL_EN;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Enables or disables the timer's internal clock.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param en Enable or disable the internal clock
|
||||
*/
|
||||
void timer_clock_enable(uint32_t timer, bool en)
|
||||
{
|
||||
if (timer == TIMER_SE1) {
|
||||
if (en) {
|
||||
SYSCTL_SYS_CFG_1 |= SYSCTL_SYS_CFG_1_TIMERSE1;
|
||||
} else {
|
||||
SYSCTL_SYS_CFG_1 &= ~SYSCTL_SYS_CFG_1_TIMERSE1;
|
||||
}
|
||||
} else {
|
||||
if (en) {
|
||||
SYSCTL_SYS_CFG_1 |= SYSCTL_SYS_CFG_1_TIMERSE0;
|
||||
} else {
|
||||
SYSCTL_SYS_CFG_1 &= ~SYSCTL_SYS_CFG_1_TIMERSE0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Selects the mode of operation.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param mode The mode of operation @ref timer_operation_modes
|
||||
*/
|
||||
void timer_operation_mode(uint32_t timer, enum timer_operation_modes mode)
|
||||
{
|
||||
mode = (mode << 4);
|
||||
TIMER_CTRL(timer) = (~TIMER_OPER_MODE_MASK & TIMER_CTRL(timer)) | mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* Selects the output mode.
|
||||
* Only used in counter mode.
|
||||
* When done counting, the pin can be set to no output,
|
||||
* to invert the current pin level, to set the pin high,
|
||||
* or to set the pin low.
|
||||
* @note Be sure to set the alternate functions of the timer pins
|
||||
* with @ref syscon_sel_af() and disable SWD on those pins
|
||||
* with @ref syscon_sel_swd() as needed.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param mode The output mode @ref timer_output_modes
|
||||
*/
|
||||
void timer_output_mode(uint32_t timer, enum timer_output_modes mode)
|
||||
{
|
||||
mode = (mode << 12);
|
||||
TIMER_CTRL(timer) = (~TIMER_OUTP_MODE_MASK & TIMER_CTRL(timer)) | mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* Selects the initial output level.
|
||||
* Only used in counter and PWM modes.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param level The initial output level @ref timer_level
|
||||
*/
|
||||
void timer_output_level(uint32_t timer, enum timer_level level)
|
||||
{
|
||||
TIMER_OUTPVAL(timer) = level;
|
||||
}
|
||||
|
||||
/**
|
||||
* Selects the edge mode.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param mode The edge mode @ref timer_edge_modes
|
||||
*/
|
||||
void timer_edge_mode(uint32_t timer, enum timer_edge_modes mode)
|
||||
{
|
||||
if (mode) {
|
||||
TIMER_CTRL(timer) |= TIMER_CTRL_TMOD;
|
||||
} else {
|
||||
TIMER_CTRL(timer) &= ~TIMER_CTRL_TMOD;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Selects the loop mode.
|
||||
* This has no use in PWM mode.
|
||||
* In loop mode with counter mode, the counter will constantly loop.
|
||||
* In loop mode with the capture modes, the values will be captured
|
||||
* again and again. In single mode, these operations happen only once.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param mode The loop mode @ref timer_loop_modes
|
||||
*/
|
||||
void timer_loop_mode(uint32_t timer, enum timer_loop_modes mode)
|
||||
{
|
||||
if (mode) {
|
||||
TIMER_CTRL(timer) |= TIMER_CTRL_LMOD;
|
||||
} else {
|
||||
TIMER_CTRL(timer) &= ~TIMER_CTRL_LMOD;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Selects the clock source for the timer.
|
||||
* @note Be sure to set the alternate functions of the timer pins
|
||||
* with @ref syscon_sel_af() and disable SWD on those pins
|
||||
* with @ref syscon_sel_swd() as needed.
|
||||
* @note If not using the internal clock, you can disable it
|
||||
* with @ref timer_clock_enable() for power savings.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param src Select the internal or external clock source @ref timer_clk_src
|
||||
*/
|
||||
void timer_clock_source(uint32_t timer, enum timer_clk_src src)
|
||||
{
|
||||
if (src) {
|
||||
TIMER_CTRL(timer) |= TIMER_CTRL_OSCMOD;
|
||||
} else {
|
||||
TIMER_CTRL(timer) &= ~TIMER_CTRL_OSCMOD;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets the target values for counter mode.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param target The value to count up to
|
||||
*/
|
||||
void timer_counter_target_value(uint32_t timer, uint32_t target)
|
||||
{
|
||||
TIMER_TARVAL(timer) = target;
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets the target values for PWM mode.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param period0 length of period 0 in clock cycles. Whether
|
||||
* it is high or low is set in @ref timer_output_level()
|
||||
* @param period1 length of period 1
|
||||
*/
|
||||
void timer_pwm_target_value(uint32_t timer, uint16_t period0, uint16_t period1)
|
||||
{
|
||||
timer_counter_target_value(timer, (period1 << 16) | period0);
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable or disable the interrupt.
|
||||
* In counter mode, when the count has been completed,
|
||||
* an interrupt is generated.
|
||||
* In PWM mode, on a level change, an interupt is generated.
|
||||
* In either capture mode, when a capture is complete,
|
||||
* an interrupt is generated.
|
||||
* @note If interrupts are enabled here, the interrupt should also be enabled
|
||||
* using the NVIC before enabling the timer.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param en Enable or disable the interrupt
|
||||
*/
|
||||
void timer_int_enable(uint32_t timer, bool en)
|
||||
{
|
||||
if (en) {
|
||||
TIMER_INTCTL(timer) |= TIMER_INTCTL_INTEN;
|
||||
} else {
|
||||
TIMER_INTCTL(timer) &= ~TIMER_INTCTL_INTEN;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets the interrupt mask.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @param masked Whether or not to mask the interrupt @ref timer_int_masked
|
||||
*/
|
||||
void timer_int_mask(uint32_t timer, enum timer_int_masked masked)
|
||||
{
|
||||
if (masked) {
|
||||
TIMER_INTCTL(timer) &= ~TIMER_INTCTL_INTMSK;
|
||||
} else {
|
||||
TIMER_INTCTL(timer) |= TIMER_INTCTL_INTMSK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Gets the current counter value, and clears the interrupt/interrupt overflow.
|
||||
* If in PWM mode, this is only used for clearing the interrupt.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @return The current counter value
|
||||
*/
|
||||
uint32_t timer_get_current_value(uint32_t timer)
|
||||
{
|
||||
return TIMER_CURVAL(timer);
|
||||
}
|
||||
|
||||
/**
|
||||
* Gets the cycle width.
|
||||
* Only used in duty cycle capture mode.
|
||||
* @note See the datasheet for more concise diagrams.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @return The cycle width
|
||||
*/
|
||||
uint32_t timer_get_cycle_width(uint32_t timer)
|
||||
{
|
||||
return TIMER_CAPW(timer);
|
||||
}
|
||||
|
||||
/**
|
||||
* Gets the pulse width in pulse capture mode,
|
||||
* or gets the period width in duty cycle capture mode.
|
||||
* @note See the datasheet for more concise diagrams.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @return The pulse width
|
||||
*/
|
||||
uint32_t timer_get_pulse_width(uint32_t timer)
|
||||
{
|
||||
return TIMER_CAPLH(timer);
|
||||
}
|
||||
|
||||
/**
|
||||
* Gets the current output period in PWM mode.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @return The current output period @ref timer_pwm_period
|
||||
*/
|
||||
enum timer_pwm_period timer_get_pwm_period(uint32_t timer)
|
||||
{
|
||||
return TIMER_MOD2LF(timer) & 0x1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Gets the interrupt status after masking.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @return The interrupt status after masking
|
||||
*/
|
||||
bool timer_int_status(uint32_t timer)
|
||||
{
|
||||
return TIMER_INTMSKSTAT(timer) & 0x1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Gets the interrupt status before masking.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @return The interrupt status before masking
|
||||
*/
|
||||
bool timer_int_raw_status(uint32_t timer)
|
||||
{
|
||||
return TIMER_INTSTAT(timer) & 0x1;
|
||||
}
|
||||
|
||||
/**
|
||||
* Gets the interrupt overflow status.
|
||||
* Overflow will occur if the interrupt has not been cleared when a second
|
||||
* interrupt happens.
|
||||
* @param timer Select timer @ref timer_select
|
||||
* @return The interrupt overflow status
|
||||
*/
|
||||
bool timer_int_overflow_status(uint32_t timer)
|
||||
{
|
||||
return TIMER_INTFLAG(timer) & 0x1;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
Loading…
x
Reference in New Issue
Block a user