From f0bace7838ce8c90321dc3df3f6a2936344332ae Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Mon, 29 Apr 2013 08:57:44 -0700 Subject: [PATCH] sam3x support. --- Makefile | 2 +- include/libopencm3/dispatch/nvic.h | 3 + include/libopencm3/sam3x/eefc.h | 73 +++++++++++++++ include/libopencm3/sam3x/gpio.h | 38 ++++++++ include/libopencm3/sam3x/irq.yaml | 49 ++++++++++ include/libopencm3/sam3x/memorymap.h | 78 ++++++++++++++++ include/libopencm3/sam3x/pio.h | 96 +++++++++++++++++++ include/libopencm3/sam3x/pmc.h | 132 +++++++++++++++++++++++++++ include/libopencm3/sam3x/pwm.h | 81 ++++++++++++++++ include/libopencm3/sam3x/tc.h | 52 +++++++++++ include/libopencm3/sam3x/uart.h | 85 +++++++++++++++++ include/libopencm3/sam3x/wdt.h | 57 ++++++++++++ lib/dispatch/vector_nvic.c | 3 + lib/sam3x/Makefile | 36 ++++++++ lib/sam3x/gpio.c | 38 ++++++++ lib/sam3x/libopencm3_sam3x.ld | 106 +++++++++++++++++++++ lib/sam3x/pio.c | 28 ++++++ lib/sam3x/pmc.c | 44 +++++++++ 18 files changed, 1000 insertions(+), 1 deletion(-) create mode 100644 include/libopencm3/sam3x/eefc.h create mode 100644 include/libopencm3/sam3x/gpio.h create mode 100644 include/libopencm3/sam3x/irq.yaml create mode 100644 include/libopencm3/sam3x/memorymap.h create mode 100644 include/libopencm3/sam3x/pio.h create mode 100644 include/libopencm3/sam3x/pmc.h create mode 100644 include/libopencm3/sam3x/pwm.h create mode 100644 include/libopencm3/sam3x/tc.h create mode 100644 include/libopencm3/sam3x/uart.h create mode 100644 include/libopencm3/sam3x/wdt.h create mode 100644 lib/sam3x/Makefile create mode 100644 lib/sam3x/gpio.c create mode 100644 lib/sam3x/libopencm3_sam3x.ld create mode 100644 lib/sam3x/pio.c create mode 100644 lib/sam3x/pmc.c diff --git a/Makefile b/Makefile index b844815b..5ee65f02 100644 --- a/Makefile +++ b/Makefile @@ -32,7 +32,7 @@ SHAREDIR = $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts INSTALL = install SRCLIBDIR = $(shell pwd)/lib -TARGETS = stm32/f1 stm32/f2 stm32/f4 stm32/l1 lpc13xx lpc17xx lpc43xx lm3s lm4f efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg +TARGETS = stm32/f1 stm32/f2 stm32/f4 stm32/l1 lpc13xx lpc17xx lpc43xx lm3s lm4f efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg sam3x # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index c671d094..fe0bd05a 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -23,6 +23,9 @@ #elif defined(LPC43XX) # include +#elif defined(SAM3X) +# include + #elif defined(LM3S) || defined(LM4F) /* Yes, we use the same interrupt table for both LM3S and LM4F */ # include diff --git a/include/libopencm3/sam3x/eefc.h b/include/libopencm3/sam3x/eefc.h new file mode 100644 index 00000000..a2adf7e5 --- /dev/null +++ b/include/libopencm3/sam3x/eefc.h @@ -0,0 +1,73 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_EEFC_H +#define SAM3X_EEFC_H + +#include +#include + +/* --- Convenience macros ------------------------------------------------ */ +#define EEFC0 EEFC0_BASE +#define EEFC1 EEFC1_BASE + +/* --- Enhanced Embedded Flash Controller (EEFC) registers --------------- */ +#define EEFC_FMR(port) MMIO32((port) + 0x00) +#define EEFC_FCR(port) MMIO32((port) + 0x04) +#define EEFC_FSR(port) MMIO32((port) + 0x08) +#define EEFC_FRR(port) MMIO32((port) + 0x0C) +/* 0x0010 - Reserved */ + + +/* EEFC Flash Mode Register (EEFC_FMR) */ +/* Bit [31:25] - Reserved */ +#define EEFC_FMR_FAM (0x01 << 24) +/* Bit [23:12] - Reserved */ +#define EEFC_FMR_FWS_MASK (0x0F << 8) +/* Bit [7:1] - Reserved */ +#define EEFC_FMR_FRDY (0x01 << 0) + +/* EEFC Flash Command Register (EEFC_FCR) */ +#define EEFC_FCR_FKEY (0x5A << 24) +#define EEFC_FCR_FARG_MASK (0xFFFF << 8) +#define EEFC_FCR_FCMD_MASK (0xFF << 0) +#define EEFC_FCR_FCMD_GETD (0x00 << 0) +#define EEFC_FCR_FCMD_WP (0x01 << 0) +#define EEFC_FCR_FCMD_WPL (0x02 << 0) +#define EEFC_FCR_FCMD_EWP (0x03 << 0) +#define EEFC_FCR_FCMD_EWPL (0x04 << 0) +#define EEFC_FCR_FCMD_EA (0x05 << 0) +#define EEFC_FCR_FCMD_SLB (0x08 << 0) +#define EEFC_FCR_FCMD_CLB (0x09 << 0) +#define EEFC_FCR_FCMD_GLB (0x0A << 0) +#define EEFC_FCR_FCMD_SGPB (0x0B << 0) +#define EEFC_FCR_FCMD_CGPB (0x0C << 0) +#define EEFC_FCR_FCMD_GGPB (0x0D << 0) +#define EEFC_FCR_FCMD_STUI (0x0E << 0) +#define EEFC_FCR_FCMD_SPUI (0x0F << 0) + +/* EEFC Flash Status Register (EEFC_FSR) */ +/* Bit [31:3] - Reserved */ +#define EEFC_FSR_FLOCKE (0x01 << 2) +#define EEFC_FSR_FCMDE (0x01 << 1) +#define EEFC_FSR_FRDY (0x01 << 0) + + +#endif + diff --git a/include/libopencm3/sam3x/gpio.h b/include/libopencm3/sam3x/gpio.h new file mode 100644 index 00000000..ce3e6120 --- /dev/null +++ b/include/libopencm3/sam3x/gpio.h @@ -0,0 +1,38 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_GPIO_H +#define SAM3X_GPIO_H + +#include + +static inline void gpio_set(u32 gpioport, u32 gpios) +{ + PIO_SODR(gpioport) = gpios; +} + +void gpio_clear(u32 gpioport, u32 gpios) +{ + PIO_CODR(gpioport) = gpios; +} + +void gpio_toggle(u32 gpioport, u32 gpios); + +#endif + diff --git a/include/libopencm3/sam3x/irq.yaml b/include/libopencm3/sam3x/irq.yaml new file mode 100644 index 00000000..8d163066 --- /dev/null +++ b/include/libopencm3/sam3x/irq.yaml @@ -0,0 +1,49 @@ +includeguard: LIBOPENCM3_SAM3X_NVIC_H +partname_humanreadable: Atmel SAM3X series +partname_doxygen: SAM3X +irqs: + - supc + - rstc + - rtc + - rtt + - wdg + - pmc + - eefc0 + - eefc1 + - uart + - smc_sdramc + - sdramc + - pioa + - piob + - pioc + - piod + - pioe + - piof + - usart0 + - usart1 + - usart2 + - usart3 + - hsmci + - twi0 + - twi1 + - spi0 + - spi1 + - ssc + - tc0 + - tc1 + - tc2 + - tc3 + - tc4 + - tc5 + - tc6 + - tc7 + - tc8 + - pwm + - adc + - dacc + - dmac + - uotghs + - trng + - emac + - can0 + - can1 diff --git a/include/libopencm3/sam3x/memorymap.h b/include/libopencm3/sam3x/memorymap.h new file mode 100644 index 00000000..ca0bb1a5 --- /dev/null +++ b/include/libopencm3/sam3x/memorymap.h @@ -0,0 +1,78 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_MEMORYMAP_H +#define SAM3X_MEMORYMAP_H + +#include + +/* --- SAM3X peripheral space -------------------------------------------- */ + +#define HSMCI_BASE (0x40000000) +#define SSC_BASE (0x40004000) +#define SPI0_BASE (0x40008000) +#define SPI1_BASE (0x4000C000) +#define TC0_BASE (0x40080000) +#define TC1_BASE (0x40080040) +#define TC2_BASE (0x40080080) +#define TC3_BASE (0x40084000) +#define TC4_BASE (0x40084040) +#define TC5_BASE (0x40084080) +#define TC6_BASE (0x40088000) +#define TC7_BASE (0x40088040) +#define TC8_BASE (0x40088080) +#define TWI0_BASE (0x4008C000) +#define TWI1_BASE (0x40090000) +#define PWM_BASE (0x40094000) +#define USART0_BASE (0x40098000) +#define USART1_BASE (0x4009C000) +#define USART2_BASE (0x400A0000) +#define USART3_BASE (0x400A4000) +#define UOTGHS_BASE (0x400AC000) +#define EMAC_BASE (0x400B0000) +#define CAN0_BASE (0x400B4000) +#define CAN1_BASE (0x400B8000) +#define TRNG_BASE (0x400BC000) +#define ADC_BASE (0x400C0000) +#define DMAC_BASE (0x400C4000) + +/* --- SAM3X system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000) +#define SDRAM_BASE (0x400E0200) +#define MATRIX_BASE (0x400E0400) +#define PMC_BASE (0x400E0600) +#define UART_BASE (0x400E0800) +#define CHIPID_BASE (0x400E0940) +#define EEFC0_BASE (0x400E0A00) +#define EEFC1_BASE (0x400E0C00) +#define PIOA_BASE (0x400E0E00) +#define PIOB_BASE (0x400E1000) +#define PIOC_BASE (0x400E1200) +#define PIOD_BASE (0x400E1400) +#define PIOE_BASE (0x400E1600) +#define PIOF_BASE (0x400E1800) +#define RSTC_BASE (0x400E1A00) +#define SUPC_BASE (0x400E1A10) +#define RTT_BASE (0x400E1A30) +#define WDT_BASE (0x400E1A50) +#define RTC_BASE (0x400E1A60) +#define GPBR_BASE (0x400E1A90) +#define RTC_BASE (0x400E1A60) + +#endif diff --git a/include/libopencm3/sam3x/pio.h b/include/libopencm3/sam3x/pio.h new file mode 100644 index 00000000..d3a76bcd --- /dev/null +++ b/include/libopencm3/sam3x/pio.h @@ -0,0 +1,96 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_PIO_H +#define SAM3X_PIO_H + +#include +#include + +/* --- Convenience macros ------------------------------------------------ */ + +/* GPIO port base addresses (for convenience) */ +#define PIOA PIOA_BASE +#define PIOB PIOB_BASE +#define PIOC PIOC_BASE +#define PIOD PIOD_BASE +#define PIOE PIOE_BASE +#define PIOF PIOF_BASE +#define PIOG PIOG_BASE +#define PIOH PIOH_BASE + +/* --- PIO registers ----------------------------------------------------- */ + +#define PIO_PER(port) MMIO32((port) + 0x0000) +#define PIO_PDR(port) MMIO32((port) + 0x0004) +#define PIO_PSR(port) MMIO32((port) + 0x0008) +/* 0x000C - Reserved */ +#define PIO_OER(port) MMIO32((port) + 0x0010) +#define PIO_ODR(port) MMIO32((port) + 0x0014) +#define PIO_OSR(port) MMIO32((port) + 0x0018) +/* 0x001C - Reserved */ +#define PIO_IFER(port) MMIO32((port) + 0x0020) +#define PIO_IFDR(port) MMIO32((port) + 0x0024) +#define PIO_IFSR(port) MMIO32((port) + 0x0028) +/* 0x002C - Reserved */ +#define PIO_SODR(port) MMIO32((port) + 0x0030) +#define PIO_CODR(port) MMIO32((port) + 0x0034) +#define PIO_ODSR(port) MMIO32((port) + 0x0038) +#define PIO_PDSR(port) MMIO32((port) + 0x003C) +#define PIO_IER(port) MMIO32((port) + 0x0040) +#define PIO_IDR(port) MMIO32((port) + 0x0044) +#define PIO_IMR(port) MMIO32((port) + 0x0048) +#define PIO_ISR(port) MMIO32((port) + 0x004C) +#define PIO_MDER(port) MMIO32((port) + 0x0050) +#define PIO_MDDR(port) MMIO32((port) + 0x0054) +#define PIO_MDSR(port) MMIO32((port) + 0x0058) +/* 0x005C - Reserved */ +#define PIO_PUDR(port) MMIO32((port) + 0x0060) +#define PIO_PUER(port) MMIO32((port) + 0x0064) +#define PIO_PUSR(port) MMIO32((port) + 0x0068) +/* 0x006C - Reserved */ +#define PIO_ABSR(port) MMIO32((port) + 0x0070) +/* 0x0074-0x007C - Reserved */ +#define PIO_SCIFSR(port) MMIO32((port) + 0x0080) +#define PIO_DIFSR(port) MMIO32((port) + 0x0084) +#define PIO_IFDGSR(port) MMIO32((port) + 0x0088) +#define PIO_SCDR(port) MMIO32((port) + 0x008C) +/* 0x0090-0x009C - Reserved */ +#define PIO_OWER(port) MMIO32((port) + 0x00A0) +#define PIO_OWDR(port) MMIO32((port) + 0x00A4) +#define PIO_OWSR(port) MMIO32((port) + 0x00A8) +/* 0x00AC - Reserved */ +#define PIO_AIMER(port) MMIO32((port) + 0x00B0) +#define PIO_AIMDR(port) MMIO32((port) + 0x00B4) +#define PIO_AIMMR(port) MMIO32((port) + 0x00B8) +/* 0x00BC - Reserved */ +#define PIO_ESR(port) MMIO32((port) + 0x00C0) +#define PIO_LSR(port) MMIO32((port) + 0x00C4) +#define PIO_ELSR(port) MMIO32((port) + 0x00C8) +/* 0x00CC - Reserved */ +#define PIO_FELLSR(port) MMIO32((port) + 0x00D0) +#define PIO_REHLSR(port) MMIO32((port) + 0x00D4) +#define PIO_FRLHSR(port) MMIO32((port) + 0x00D8) +/* 0x00DC - Reserved */ +#define PIO_LOCKSR(port) MMIO32((port) + 0x00E0) +#define PIO_WPMR(port) MMIO32((port) + 0x00E4) +#define PIO_WPSR(port) MMIO32((port) + 0x00E8) +/* 0x00EC-0x0144 - Reserved */ + +#endif diff --git a/include/libopencm3/sam3x/pmc.h b/include/libopencm3/sam3x/pmc.h new file mode 100644 index 00000000..9b4b63ee --- /dev/null +++ b/include/libopencm3/sam3x/pmc.h @@ -0,0 +1,132 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_PMC_H +#define SAM3X_PMC_H + +#include +#include + +/* --- Power Management Controller (PMC) registers ----------------------- */ + +#define PMC_SCER MMIO32(PMC_BASE + 0x0000) +#define PMC_SCDR MMIO32(PMC_BASE + 0x0004) +#define PMC_SCSR MMIO32(PMC_BASE + 0x0008) +/* 0x000C - Reserved */ +#define PMC_PCER0 MMIO32(PMC_BASE + 0x0010) +#define PMC_PCDR0 MMIO32(PMC_BASE + 0x0014) +#define PMC_PCSR0 MMIO32(PMC_BASE + 0x0018) +#define CKGR_UCKR MMIO32(PMC_BASE + 0x001C) +#define CKGR_MOR MMIO32(PMC_BASE + 0x0020) +#define CKGR_MCFR MMIO32(PMC_BASE + 0x0024) +#define CKGR_PLLAR MMIO32(PMC_BASE + 0x0028) +/* 0x002C - Reserved */ +#define PMC_MCKR MMIO32(PMC_BASE + 0x0030) +/* 0x0034 - Reserved */ +#define PMC_USB MMIO32(PMC_BASE + 0x0038) +/* 0x003C - Reserved */ +#define PMC_PCK0 MMIO32(PMC_BASE + 0x0040) +#define PMC_PCK1 MMIO32(PMC_BASE + 0x0044) +#define PMC_PCK2 MMIO32(PMC_BASE + 0x0048) +/* 0x004C-0x005C - Reserved */ +#define PMC_IER MMIO32(PMC_BASE + 0x0060) +#define PMC_IDR MMIO32(PMC_BASE + 0x0064) +#define PMC_SR MMIO32(PMC_BASE + 0x0068) +#define PMC_IMR MMIO32(PMC_BASE + 0x006C) +#define PMC_FSMR MMIO32(PMC_BASE + 0x0070) +#define PMC_FSPR MMIO32(PMC_BASE + 0x0074) +#define PMC_FOCR MMIO32(PMC_BASE + 0x0078) +/* 0x007C-0x00E0 - Reserved */ +#define PMC_WPMR MMIO32(PMC_BASE + 0x00E4) +#define PMC_WPSR MMIO32(PMC_BASE + 0x00E8) +/* 0x00EC-0x00FC - Reserved */ +#define PMC_PCER1 MMIO32(PMC_BASE + 0x0100) +#define PMC_PCDR1 MMIO32(PMC_BASE + 0x0104) +#define PMC_PCSR1 MMIO32(PMC_BASE + 0x0108) +#define PMC_PCR MMIO32(PMC_BASE + 0x010C) + +/* PMC UTMI Clock Configuration Register (CKGR_UCKR) */ +/* Bit [31:22] - Reserved */ +#define CKGR_CKGR_UPLLCOUNT_MASK (0x0F << 20) +/* Bit [19:17] - Reserved */ +#define CKGR_CKGR_UPLLEN (0x01 << 16) +/* Bit [15:0] - Reserved */ + +/* PMC Clock Generator Main Oscillator Register (CKGR_MOR) */ +/* Bit [31:26] - Reserved */ +#define CKGR_MOR_CFDEN (0x01 << 25) +#define CKGR_MOR_MOSCSEL (0x01 << 24) +#define CKGR_MOR_KEY (0x37 << 16) +#define CKGR_MOR_MOSCXTST_MASK (0xFF << 8) +/* Bit 7 - Reserved */ +#define CKGR_MOR_MOSCRCF_MASK (0x07 << 4) +#define CKGR_MOR_MOSCRCEN (0x01 << 3) +/* Bit 2 - Reserved */ +#define CKGR_MOR_MOSCXTBY (0x01 << 1) +#define CKGR_MOR_MOSCXTEN (0x01 << 0) + +/* PMC Clock Generator PLLA Register (CKGR_PLLAR) */ +#define CKGR_PLLAR_ONE (0x01 << 29) +#define CKGR_PLLAR_MULA_MASK (0x7FF << 16) +#define CKGR_PLLAR_PLLACOUNT_MASK (0x3F << 8) +#define CKGR_PLLAR_DIVA_MASK (0xFF << 0) + +/* PMC Master Clock Register (PMC_MCKR) */ +/* Bit [31:14] - Reserved */ +#define PMC_MCKR_UPLLDIV2 (0x01 << 13) +#define PMC_MCKR_PLLADIV2 (0x01 << 12) +/* Bit [11:7] - Reserved */ +#define PMC_MCKR_PRES_MASK (0x07 << 4) +/* Bit [3:2] - Reserved */ +#define PMC_MCKR_CSS_MASK (0x03 << 0) +#define PMC_MCKR_CSS_SLOW_CLK (0x00 << 0) +#define PMC_MCKR_CSS_MAIN_CLK (0x01 << 0) +#define PMC_MCKR_CSS_PLLA_CLK (0x02 << 0) +#define PMC_MCKR_CSS_UPLL_CLK (0x03 << 0) + +/* PMC USB Clock Register (PMC_USB) */ +/* Bit [31:12] - Reserved */ +#define PMC_USB_USBDIV_MASK (0x0F << 8) +/* Bit [7:1] - Reserved */ +#define PMC_USB_USBS (0x01 << 0) + +/* PMC Status Register (PMC_SR) */ +/* Bits [31:21] - Reserved */ +#define PMC_SR_FOS (0x01 << 20) +#define PMC_SR_CFDS (0x01 << 19) +#define PMC_SR_CFDEV (0x01 << 18) +#define PMC_SR_MOSCRCS (0x01 << 17) +#define PMC_SR_MOSCSELS (0x01 << 16) +/* Bits [15:11] - Reserved */ +#define PMC_SR_PCKRDY2 (0x01 << 10) +#define PMC_SR_PCKRDY1 (0x01 << 9) +#define PMC_SR_PCKRDY0 (0x01 << 8) +#define PMC_SR_OSCSELS (0x01 << 7) +#define PMC_SR_LOCKU (0x01 << 6) +/* Bits [5:4] - Reserved */ +#define PMC_SR_MCKRDY (0x01 << 3) +/* Bit [2] - Reserved */ +#define PMC_SR_LOCKA (0x01 << 1) +#define PMC_SR_MOSCXTS (0x01 << 0) + +void pmc_plla_config(u8 mul, u8 div); +void pmc_peripheral_clock_enable(u8 pid); +void pmc_peripheral_clock_disable(u8 pid); + +#endif diff --git a/include/libopencm3/sam3x/pwm.h b/include/libopencm3/sam3x/pwm.h new file mode 100644 index 00000000..a911cbf3 --- /dev/null +++ b/include/libopencm3/sam3x/pwm.h @@ -0,0 +1,81 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_PWM_H +#define SAM3X_PWM_H + +#include +#include + +/* --- Pulse Width Modulation (PWM) registers ----------------------- */ + +#define PWM_CLK MMIO32(PWM_BASE + 0x0000) +#define PWM_ENA MMIO32(PWM_BASE + 0x0004) +#define PWM_DIS MMIO32(PWM_BASE + 0x0008) +#define PWM_SR MMIO32(PWM_BASE + 0x000C) +#define PWM_IER1 MMIO32(PWM_BASE + 0x0010) +#define PWM_IDR1 MMIO32(PWM_BASE + 0x0014) +#define PWM_IMR1 MMIO32(PWM_BASE + 0x0018) +#define PWM_ISR1 MMIO32(PWM_BASE + 0x001C) +#define PWM_SCM MMIO32(PWM_BASE + 0x0020) +/* 0x0024 - Reserved */ +#define PWM_SCUC MMIO32(PWM_BASE + 0x0028) +#define PWM_SCUP MMIO32(PWM_BASE + 0x002C) +#define PWM_SCUPUPD MMIO32(PWM_BASE + 0x0030) +#define PWM_IER2 MMIO32(PWM_BASE + 0x0034) +#define PWM_IDR2 MMIO32(PWM_BASE + 0x0038) +#define PWM_IMR2 MMIO32(PWM_BASE + 0x003C) +#define PWM_ISR2 MMIO32(PWM_BASE + 0x0040) +#define PWM_OOV MMIO32(PWM_BASE + 0x0044) +#define PWM_OS MMIO32(PWM_BASE + 0x0048) +#define PWM_OSS MMIO32(PWM_BASE + 0x004C) +#define PWM_OSC MMIO32(PWM_BASE + 0x0050) +#define PWM_OSSUPD MMIO32(PWM_BASE + 0x0054) +#define PWM_OSCUPD MMIO32(PWM_BASE + 0x0058) +#define PWM_FMR MMIO32(PWM_BASE + 0x005C) +#define PWM_FSR MMIO32(PWM_BASE + 0x0060) +#define PWM_FCR MMIO32(PWM_BASE + 0x0064) +#define PWM_FPV MMIO32(PWM_BASE + 0x0068) +#define PWM_FPE1 MMIO32(PWM_BASE + 0x006C) +#define PWM_FPE2 MMIO32(PWM_BASE + 0x0070) +/* 0x0074:0x0078 - Reserved */ +#define PWM_ELMR0 MMIO32(PWM_BASE + 0x007C) +#define PWM_ELMR1 MMIO32(PWM_BASE + 0x0080) +/* 0x0084:0x00AC - Reserved */ +#define PWM_SMMR MMIO32(PWM_BASE + 0x00B0) +/* 0x00B4:0x00E0 - Reserved */ +#define PWM_WPCR MMIO32(PWM_BASE + 0x00E4) +#define PWM_WPSR MMIO32(PWM_BASE + 0x00E8) +/* 0x00EC:0x00FC - Reserved */ +/* 0x0100:0x012C - Reserved */ +#define PWM_CMPV(x) MMIO32(PWM_BASE + 0x0130 + 0x10*(x)) +#define PWM_CMPVUPD(x) MMIO32(PWM_BASE + 0x0134 + 0x10*(x)) +#define PWM_CMMV(x) MMIO32(PWM_BASE + 0x0138 + 0x10*(x)) +#define PWM_CMMVUPD(x) MMIO32(PWM_BASE + 0x013C + 0x10*(x)) +/* 0x01B0:0x01FC - Reserved */ +#define PWM_CMR(x) MMIO32(PWM_BASE + 0x0200 + 0x20*(x)) +#define PWM_CDTY(x) MMIO32(PWM_BASE + 0x0204 + 0x20*(x)) +#define PWM_CDTYUPD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x)) +#define PWM_CPRD(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x)) +#define PWM_CPRDUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x)) +#define PWM_CCNT(x) MMIO32(PWM_BASE + 0x0214 + 0x20*(x)) +#define PWM_DT(x) MMIO32(PWM_BASE + 0x0218 + 0x20*(x)) +#define PWM_DTUPD(x) MMIO32(PWM_BASE + 0x021C + 0x20*(x)) + +#endif diff --git a/include/libopencm3/sam3x/tc.h b/include/libopencm3/sam3x/tc.h new file mode 100644 index 00000000..192d8f4c --- /dev/null +++ b/include/libopencm3/sam3x/tc.h @@ -0,0 +1,52 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_TC_H +#define SAM3X_TC_H + +#include +#include + +/* --- Timer Counter (TC) registers -------------------------------------- */ + +#define TC_CCR(x) MMIO32(TC_BASE + 0x00 + 0x40*(x)) +#define TC_CMR(x) MMIO32(TC_BASE + 0x04 + 0x40*(x)) +#define TC_SMMR(x) MMIO32(TC_BASE + 0x08 + 0x40*(x)) +/* 0x0C + 0x40*channel - Reserved */ +#define TC_CV(x) MMIO32(TC_BASE + 0x10 + 0x40*(x)) +#define TC_RA(x) MMIO32(TC_BASE + 0x14 + 0x40*(x)) +#define TC_RB(x) MMIO32(TC_BASE + 0x18 + 0x40*(x)) +#define TC_RC(x) MMIO32(TC_BASE + 0x1C + 0x40*(x)) +#define TC_SR(x) MMIO32(TC_BASE + 0x20 + 0x40*(x)) +#define TC_IER(x) MMIO32(TC_BASE + 0x24 + 0x40*(x)) +#define TC_IDR(x) MMIO32(TC_BASE + 0x28 + 0x40*(x)) +#define TC_IMR(x) MMIO32(TC_BASE + 0x2C + 0x40*(x)) +#define TC_BCR MMIO32(TC_BASE + 0xC0) +#define TC_BMR MMIO32(TC_BASE + 0xC4) +#define TC_QIER MMIO32(TC_BASE + 0xC8) +#define TC_QIDR MMIO32(TC_BASE + 0xCC) +#define TC_QIMR MMIO32(TC_BASE + 0xD0) +#define TC_QISR MMIO32(TC_BASE + 0xD4) +#define TC_FMR MMIO32(TC_BASE + 0xD8) +/* 0x00DC:0x00E0 - Undocumented */ +#define TC_WPMR MMIO32(TC_BASE + 0xE4) +/* 0x00E8:0x00F8 - Undocumented */ +/* 0x00FC - Reserved */ + +#endif diff --git a/include/libopencm3/sam3x/uart.h b/include/libopencm3/sam3x/uart.h new file mode 100644 index 00000000..2c8d3a21 --- /dev/null +++ b/include/libopencm3/sam3x/uart.h @@ -0,0 +1,85 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_UART_H +#define SAM3X_UART_H + +#include +#include + +/* --- Universal Asynchronous Receiver Transmitter (UART) registers ------- */ +#define UART_CR MMIO32(UART_BASE + 0x0000) +#define UART_MR MMIO32(UART_BASE + 0x0004) +#define UART_IER MMIO32(UART_BASE + 0x0008) +#define UART_IDR MMIO32(UART_BASE + 0x000C) +#define UART_IMR MMIO32(UART_BASE + 0x0010) +#define UART_SR MMIO32(UART_BASE + 0x0014) +#define UART_RHR MMIO32(UART_BASE + 0x0018) +#define UART_THR MMIO32(UART_BASE + 0x001C) +#define UART_BRGR MMIO32(UART_BASE + 0x0020) +/* 0x0024:0x003C - Reserved */ +/* 0x004C:0x00FC - Reserved */ +/* 0x0100:0x0124 - PDC Area */ + + +/* UART Control Register (UART_CR) */ +/* Bits [31:9] - Reserved */ +#define UART_CR_RSTSTA (0x01 << 8) +#define UART_CR_TXDIS (0x01 << 7) +#define UART_CR_TXEN (0x01 << 6) +#define UART_CR_RXDIS (0x01 << 5) +#define UART_CR_RXEN (0x01 << 4) +#define UART_CR_RSTTX (0x01 << 3) +#define UART_CR_RSTRX (0x01 << 2) +/* Bit [1:0] - Reserved */ + +/* UART Mode Register (UART_MR) */ +/* Bits [31:16] - Reserved */ +#define UART_MR_CHMODE_MASK (0x03 << 14) +#define UART_MR_CHMODE_NORMAL (0x00 << 14) +#define UART_MR_CHMODE_AUTOMATIC (0x01 << 14) +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14) +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14) +/* Bits [13:12] - Reserved */ +#define UART_MR_PAR_MASK (0x07 << 9) +#define UART_MR_PAR_EVEN (0x00 << 9) +#define UART_MR_PAR_ODD (0x01 << 9) +#define UART_MR_PAR_SPACE (0x02 << 9) +#define UART_MR_PAR_MARK (0x03 << 9) +#define UART_MR_PAR_NO (0x04 << 9) +/* Bits [8:0] - Reserved */ + +/* UART Status Register (UART_SR) */ +/* Bits [31:13] - Reserved */ +#define UART_SR_RXBUFF (0x01 << 12) +#define UART_SR_TXBUFF (0x01 << 11) +/* Bit [10] - Reserved */ +#define UART_SR_TXEMPTY (0x01 << 9) +/* Bit [8] - Reserved */ +#define UART_SR_PARE (0x01 << 7) +#define UART_SR_FRAME (0x01 << 6) +#define UART_SR_OVRE (0x01 << 5) +#define UART_SR_ENDTX (0x01 << 4) +#define UART_SR_ENDRX (0x01 << 3) +/* Bit [2] - Reserved */ +#define UART_SR_TXRDY (0x01 << 1) +#define UART_SR_RXRDY (0x01 << 0) + +#endif + diff --git a/include/libopencm3/sam3x/wdt.h b/include/libopencm3/sam3x/wdt.h new file mode 100644 index 00000000..c4ab2313 --- /dev/null +++ b/include/libopencm3/sam3x/wdt.h @@ -0,0 +1,57 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_WDT_H +#define SAM3X_WDT_H + +#include +#include + + +/* --- WDT registers ----------------------------------------------------- */ + +#define WDT_CR MMIO32(WDT_BASE + 0x00) +#define WDT_MR MMIO32(WDT_BASE + 0x04) +#define WDT_SR MMIO32(WDT_BASE + 0x08) + +/* --- WDT_CR values ------------------------------------------------------ */ + +#define WDT_CR_KEY (0xA5 << 24) +/* Bits [23:1]: Reserved. */ +#define WDT_CR_WDRSTT (1 << 0) + +/* --- WDT_MR values ------------------------------------------------------ */ + +/* Bits [31:32]: Reserved. */ +#define WDT_MR_WDIDLEHLT (1 << 29) +#define WDT_MR_WDDBGHLT (1 << 28) +#define WDT_MR_WDD_MASK (0xFFF << 16) +#define WDT_MR_WDDIS (1 << 15) +#define WDT_MR_WDRPROC (1 << 14) +#define WDT_MR_WDRSTEN (1 << 13) +#define WDT_MR_WDFIEN (1 << 12) +#define WDT_MR_WDV_MASK (0xFFF << 0) + +/* --- WDT_SR values ------------------------------------------------------ */ + +/* Bits [31:2]: Reserved. */ +#define WDT_SR_WDERR (1 << 1) +#define WDT_SR_WDUNF (1 << 0) + +#endif diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index 182de4c8..782aa0e4 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -23,6 +23,9 @@ #elif defined(LPC43XX) # include "../lpc43xx/vector_nvic.c" +#elif defined(SAM3X) +# include "../sam3x/vector_nvic.c" + #elif defined(LM3S) || defined(LM4F) /* Yes, we use the same interrupt table for both LM3S and LM4F */ # include "../lm3s/vector_nvic.c" diff --git a/lib/sam3x/Makefile b/lib/sam3x/Makefile new file mode 100644 index 00000000..d43f5cdf --- /dev/null +++ b/lib/sam3x/Makefile @@ -0,0 +1,36 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2009 Uwe Hermann +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see . +## + +LIBNAME = libopencm3_sam3x + +PREFIX ?= arm-none-eabi +#PREFIX ?= arm-elf +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \ + -mcpu=cortex-m3 -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DSAM3X +# ARFLAGS = rcsv +ARFLAGS = rcs +OBJS = gpio.o pmc.o + +VPATH += ../usb:../cm3 + +include ../Makefile.include + diff --git a/lib/sam3x/gpio.c b/lib/sam3x/gpio.c new file mode 100644 index 00000000..57eea1ec --- /dev/null +++ b/lib/sam3x/gpio.c @@ -0,0 +1,38 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void pio_set(u32 gpioport, u32 gpios) +{ + PIO_SODR(gpioport) = gpios; +} + +void pio_clear(u32 gpioport, u32 gpios) +{ + PIO_CODR(gpioport) = gpios; +} + +void pio_toggle(u32 gpioport, u32 gpios) +{ + u32 odsr = PIO_ODSR(gpioport); + PIO_CODR(gpioport) = odsr & gpios; + PIO_SODR(gpioport) = ~odsr & gpios; +} + diff --git a/lib/sam3x/libopencm3_sam3x.ld b/lib/sam3x/libopencm3_sam3x.ld new file mode 100644 index 00000000..3fc2ccb6 --- /dev/null +++ b/lib/sam3x/libopencm3_sam3x.ld @@ -0,0 +1,106 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Generic linker script for STM32 targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + +/* Define sections. */ +SECTIONS +{ + .text : { + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + . = ALIGN(4); + *(.rodata*) /* Read-only data */ + . = ALIGN(4); + } >rom + + /* C++ Static constructors/destructors, also used for __attribute__ + * ((constructor)) and the likes */ + .preinit_array : { + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + } >rom + .init_array : { + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + } >rom + .fini_array : { + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + } >rom + + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ + .ARM.extab : { + *(.ARM.extab*) + } >rom + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >rom + + . = ALIGN(4); + _etext = .; + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + . = ALIGN(4); + _edata = .; + } >ram AT >rom + _data_loadaddr = LOADADDR(.data); + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + . = ALIGN(4); + _ebss = .; + } >ram + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + . = ALIGN(4); + end = .; +} + +PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); + diff --git a/lib/sam3x/pio.c b/lib/sam3x/pio.c new file mode 100644 index 00000000..065bb8c0 --- /dev/null +++ b/lib/sam3x/pio.c @@ -0,0 +1,28 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void pio_toggle(u32 gpioport, u32 gpios) +{ + u32 odsr = PIO_ODSR(gpioport); + PIO_CODR(gpioport) = odsr & gpios; + PIO_SODR(gpioport) = ~odsr & gpios; +} + diff --git a/lib/sam3x/pmc.c b/lib/sam3x/pmc.c new file mode 100644 index 00000000..deeb8e1e --- /dev/null +++ b/lib/sam3x/pmc.c @@ -0,0 +1,44 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include + +void pmc_plla_config(u8 mul, u8 div) +{ + CKGR_PLLAR = CKGR_PLLAR_ONE | (mul << 16) | + CKGR_PLLAR_PLLACOUNT_MASK | div; + while (!(PMC_SR & PMC_SR_LOCKA)); +} + +void pmc_peripheral_clock_enable(u8 pid) +{ + if (pid < 32) + PMC_PCER0 = 1 << pid; + else + PMC_PCER1 = 1 << (pid & 31); +} + +void pmc_peripheral_clock_disable(u8 pid) +{ + if (pid < 32) + PMC_PCDR0 = 1 << pid; + else + PMC_PCDR1 = 1 << (pid & 31); +} +