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stm32: adc-v2: pull up regular sequence setting.

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Uses more standardized naming, fills in some missing defintions, removes some
redundant definitions.
This commit is contained in:
Karl Palsson 2016-03-03 23:30:33 +00:00
parent f9b2ffe8cf
commit f40e34680b
4 changed files with 66 additions and 119 deletions
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22
include/libopencm3/stm32/common/adc_common_v2_multi.h
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@ -145,6 +145,28 @@ specific memorymap.h header before including this header file.*/
#define ADC_CFGR1_EXTSEL_MASK (0xf << ADC_CFGR1_EXTSEL_SHIFT) #define ADC_CFGR1_EXTSEL_MASK (0xf << ADC_CFGR1_EXTSEL_SHIFT)
#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT) #define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)
/* ADC_SQRx Values: Regular Sequence ordering------------------------------- */
#define ADC_SQR1_L_SHIFT 0
#define ADC_SQR1_L_MASK 0xf
#define ADC_SQRx_SQx_MASK 0x1f
#define ADC_SQR1_SQ1_SHIFT 6
#define ADC_SQR1_SQ2_SHIFT 12
#define ADC_SQR1_SQ3_SHIFT 18
#define ADC_SQR1_SQ4_SHIFT 24
#define ADC_SQR2_SQ5_SHIFT 0
#define ADC_SQR2_SQ6_SHIFT 6
#define ADC_SQR2_SQ7_SHIFT 12
#define ADC_SQR2_SQ8_SHIFT 18
#define ADC_SQR2_SQ9_SHIFT 24
#define ADC_SQR3_SQ10_SHIFT 0
#define ADC_SQR3_SQ11_SHIFT 6
#define ADC_SQR3_SQ12_SHIFT 12
#define ADC_SQR3_SQ13_SHIFT 18
#define ADC_SQR3_SQ14_SHIFT 24
#define ADC_SQR4_SQ15_SHIFT 0
#define ADC_SQR4_SQ16_SHIFT 6
/* --- Function prototypes ------------------------------------------------- */ /* --- Function prototypes ------------------------------------------------- */
BEGIN_DECLS BEGIN_DECLS

73
include/libopencm3/stm32/f3/adc.h
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@ -235,79 +235,6 @@
/* Bit 7:0 LT3[7:0]: Analog watchdog 3 lower threshold */ /* Bit 7:0 LT3[7:0]: Analog watchdog 3 lower threshold */
/*------- ADC_SQR1 values ---------*/
#define ADC_SQR1_L_LSB 0
#define ADC_SQR1_SQ1_LSB 6
#define ADC_SQR1_SQ2_LSB 12
#define ADC_SQR1_SQ3_LSB 18
#define ADC_SQR1_SQ4_LSB 24
#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
#define ADC_SQR1_SQ1_MSK (0x1f << ADC_SQR1_SQ1_LSB)
#define ADC_SQR1_SQ2_MSK (0x1f << ADC_SQR1_SQ2_LSB)
#define ADC_SQR1_SQ3_MSK (0x1f << ADC_SQR1_SQ3_LSB)
#define ADC_SQR1_SQ4_MSK (0x1f << ADC_SQR1_SQ4_LSB)
/* Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence */
/* Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence */
/* Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence */
/* Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence */
/* L[3:0]: Regular channel sequence length */
#define ADC_SQR1_L_1_CONVERSION (0x0 << 0)
#define ADC_SQR1_L_2_CONVERSION (0x1 << 0)
#define ADC_SQR1_L_3_CONVERSION (0x2 << 0)
#define ADC_SQR1_L_4_CONVERSION (0x3 << 0)
#define ADC_SQR1_L_5_CONVERSION (0x4 << 0)
#define ADC_SQR1_L_6_CONVERSION (0x5 << 0)
#define ADC_SQR1_L_7_CONVERSION (0x6 << 0)
#define ADC_SQR1_L_8_CONVERSION (0x7 << 0)
#define ADC_SQR1_L_9_CONVERSION (0x8 << 0)
#define ADC_SQR1_L_10_CONVERSION (0x9 << 0)
#define ADC_SQR1_L_11_CONVERSION (0xA << 0)
#define ADC_SQR1_L_12_CONVERSION (0xB << 0)
#define ADC_SQR1_L_13_CONVERSION (0xC << 0)
#define ADC_SQR1_L_14_CONVERSION (0xD << 0)
#define ADC_SQR1_L_15_CONVERSION (0xE << 0)
#define ADC_SQR1_L_16_CONVERSION (0xF << 0)
/*------- ADC_SQR2 values ---------*/
/* Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence */
/* Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence */
/* Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence */
/* Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence */
/* Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence */
/*------- ADC_SQR3 values ---------*/
/* Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence */
/* Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence */
/* Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence */
/* Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence */
/* Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence */
/*------- ADC_SQR4 values ---------*/
/* Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence */
/* Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence */
/*------- ADC_DR values ---------*/ /*------- ADC_DR values ---------*/
/* Bits 15:0 RDATA[15:0]: Regular Data converted */ /* Bits 15:0 RDATA[15:0]: Regular Data converted */

44
lib/stm32/common/adc_common_v2_multi.c
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@ -83,3 +83,47 @@ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
} }
ADC_SMPR2(adc) = reg32; ADC_SMPR2(adc) = reg32;
} }
/*---------------------------------------------------------------------------*/
/** @brief ADC Set a Regular Channel Conversion Sequence
*
* Define a sequence of channels to be converted as a regular group with a
* length from 1 to 16 channels. If this is called during conversion, the
* current conversion is reset and conversion begins again with the newly
* defined group.
*
* @param[in] adc ADC block register address base @ref adc_reg_base
* @param[in] length Number of channels in the group, range 0..16
* @param[in] channel Set of channels in sequence, range @ref adc_channel
*/
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0, reg32_4 = 0;
uint8_t i = 0;
/* Maximum sequence length is 16 channels. */
if (length > 16) {
return;
}
for (i = 1; i <= length; i++) {
if (i <= 4) {
reg32_1 |= (channel[i - 1] << (i * 6));
}
if ((i > 4) & (i <= 9)) {
reg32_2 |= (channel[i - 1] << ((i - 4 - 1) * 6));
}
if ((i > 9) & (i <= 14)) {
reg32_3 |= (channel[i - 1] << ((i - 9 - 1) * 6));
}
if ((i > 14) & (i <= 16)) {
reg32_4 |= (channel[i - 1] << ((i - 14 - 1) * 6));
}
}
reg32_1 |= ((length - 1) << ADC_SQR1_L_SHIFT);
ADC_SQR1(adc) = reg32_1;
ADC_SQR2(adc) = reg32_2;
ADC_SQR3(adc) = reg32_3;
ADC_SQR4(adc) = reg32_4;
}

46
lib/stm32/f3/adc.c
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@ -488,52 +488,6 @@ void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold)
ADC_TR3(adc) = reg32; ADC_TR3(adc) = reg32;
} }
/*---------------------------------------------------------------------------*/
/** @brief ADC Set a Regular Channel Conversion Sequence
*
* Define a sequence of channels to be converted as a regular group with a
* length from 1 to 16 channels. If this is called during conversion, the
* current conversion is reset and conversion begins again with the newly
* defined group.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @param[in] length Unsigned int8. Number of channels in the group.
* @param[in] channel Unsigned int8[]. Set of channels in sequence, integers
* 0..18.
*/
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0, reg32_4 = 0;
uint8_t i = 0;
/* Maximum sequence length is 16 channels. */
if (length > 16) {
return;
}
for (i = 1; i <= length; i++) {
if (i <= 4) {
reg32_1 |= (channel[i - 1] << (i * 6));
}
if ((i > 4) & (i <= 9)) {
reg32_2 |= (channel[i - 1] << ((i - 4 - 1) * 6));
}
if ((i > 9) & (i <= 14)) {
reg32_3 |= (channel[i - 1] << ((i - 9 - 1) * 6));
}
if ((i > 14) & (i <= 16)) {
reg32_4 |= (channel[i - 1] << ((i - 14 - 1) * 6));
}
}
reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB);
ADC_SQR1(adc) = reg32_1;
ADC_SQR2(adc) = reg32_2;
ADC_SQR3(adc) = reg32_3;
ADC_SQR4(adc) = reg32_4;
}
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief ADC Set an Injected Channel Conversion Sequence /** @brief ADC Set an Injected Channel Conversion Sequence