From f4e45e74bcbb8a07dbcb13dbcb93da6885c27b2b Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Wed, 17 Oct 2012 11:47:03 -0700 Subject: [PATCH] Add a duty cycle count argument to i2c0_init() to adjust for changes in APB1 clock. --- include/libopencm3/lpc43xx/i2c.h | 2 +- lib/lpc43xx/i2c.c | 18 +++--------------- 2 files changed, 4 insertions(+), 16 deletions(-) diff --git a/include/libopencm3/lpc43xx/i2c.h b/include/libopencm3/lpc43xx/i2c.h index da92407a..2bab0b0d 100644 --- a/include/libopencm3/lpc43xx/i2c.h +++ b/include/libopencm3/lpc43xx/i2c.h @@ -151,7 +151,7 @@ LGPL License Terms @ref lgpl_license BEGIN_DECLS -void i2c0_init(void); +void i2c0_init(const uint16_t duty_cycle_count); void i2c0_tx_start(void); void i2c0_tx_byte(uint8_t byte); uint8_t i2c0_rx_byte(void); diff --git a/lib/lpc43xx/i2c.c b/lib/lpc43xx/i2c.c index 9fa36489..0d6c4c67 100644 --- a/lib/lpc43xx/i2c.c +++ b/lib/lpc43xx/i2c.c @@ -41,25 +41,13 @@ LGPL License Terms @ref lgpl_license #include #include -void i2c0_init(void) +void i2c0_init(const uint16_t duty_cycle_count) { /* enable input on SCL and SDA pins */ SCU_SFSI2C0 = SCU_I2C0_NOMINAL; - /* use IRC as clock source for APB1 (including I2C0) */ - CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC); - - /* FIXME assuming we're on IRC at 12 MHz */ - - /* 400 kHz I2C */ - I2C0_SCLH = 15; - I2C0_SCLL = 15; - - /* 100 kHz I2C */ - /* - I2C0_SCLH = 60; - I2C0_SCLL = 60; - */ + I2C0_SCLH = duty_cycle_count; + I2C0_SCLL = duty_cycle_count; /* clear the control bits */ I2C0_CONCLR = (I2C_CONCLR_AAC | I2C_CONCLR_SIC