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lm4f: Properly set PLL divisor

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rcc_set_pll_divisor() would take the number we wanted to divide the 400MHz
clock and put it directly in the RCC2 register. This caused the clock to always
be one speed tier slower than expected. The value of the divisor must be
decremented by 1, so a divisor of 5 will be written as 4 in the RCC2.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Alexandru Gagniuc 2013-05-07 01:59:10 -05:00
parent af98521301
commit f4eca5400e
1 changed files with 1 additions and 1 deletions
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lib/lm4f/rcc.c
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@ -277,7 +277,7 @@ void rcc_set_pll_divisor(u8 div400)
reg32 = SYSCTL_RCC2;
reg32 &= ~SYSCTL_RCC2_SYSDIV400_MASK;
reg32 |= (div400 << 22) & SYSCTL_RCC2_SYSDIV400_MASK;
reg32 |= ((div400 - 1) << 22) & SYSCTL_RCC2_SYSDIV400_MASK;
/* We are expecting a divider from 400MHz */
reg32 |= SYSCTL_RCC2_DIV400;
SYSCTL_RCC2 = reg32;