From f622437cfb2575d32be4aeac8bef25cb7ba183ff Mon Sep 17 00:00:00 2001 From: Onno Kortmann Date: Wed, 4 Dec 2013 22:43:28 -0800 Subject: [PATCH] STM32F0: Fix PLL multiplication factor for 48MHz setup It was set to overclocking configuration! --- lib/stm32/f0/rcc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/stm32/f0/rcc.c b/lib/stm32/f0/rcc.c index 69bdbd88..5d14df42 100644 --- a/lib/stm32/f0/rcc.c +++ b/lib/stm32/f0/rcc.c @@ -587,8 +587,8 @@ void rcc_clock_setup_in_hsi_out_48mhz(void) flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ); - /* 8MHz * 12 / 2 = 24MHz */ - rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL16); + /* 8MHz * 12 / 2 = 48MHz */ + rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL12); RCC_CFGR &= RCC_CFGR_PLLSRC;