diff --git a/include/libopencm3/stm32/common/adc_common_v2.h b/include/libopencm3/stm32/common/adc_common_v2.h index 6acacc86..4c3a9cb7 100644 --- a/include/libopencm3/stm32/common/adc_common_v2.h +++ b/include/libopencm3/stm32/common/adc_common_v2.h @@ -35,10 +35,133 @@ specific memorymap.h header before including this header file.*/ #ifndef LIBOPENCM3_ADC_COMMON_V2_H #define LIBOPENCM3_ADC_COMMON_V2_H +/* ----- ADC registers -----------------------------------------------------*/ +/* ADC interrupt and status register */ +#define ADC_ISR(adc) MMIO32((adc) + 0x00) +/* Interrupt Enable Register */ +#define ADC_IER(adc) MMIO32((adc) + 0x04) +/* Control Register */ +#define ADC_CR(adc) MMIO32((adc) + 0x08) +/* Configuration Register 1 */ +#define ADC_CFGR1(adc) MMIO32((adc) + 0x0C) +/* Configuration Register 2 */ +#define ADC_CFGR2(adc) MMIO32((adc) + 0x10) +/* Sample Time Register 1 */ +#define ADC_SMPR1(adc) MMIO32((adc) + 0x14) +/* Watchdog Threshold Register 1*/ +#define ADC_TR1(adc) MMIO32((adc) + 0x20) +/* Regular Data Register */ +#define ADC_DR(adc) MMIO32((adc) + 0x40) +/* CALFACT for all but f0 :(*/ + /* ADC common (shared) registers */ -#define ADC_CSR(adc) MMIO32((adc) + 0x300 + 0x0) #define ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8) -#define ADC_CDR(adc) MMIO32((adc) + 0x300 + 0xa) + +/* --- Register values -------------------------------------------------------*/ + +/* ADC_ISR Values -----------------------------------------------------------*/ + +/* AWD1: Analog watchdog 1 flag */ +#define ADC_ISR_AWD1 (1 << 7) +#define ADC_ISR_OVR (1 << 4) +#define ADC_ISR_EOS (1 << 3) +#define ADC_ISR_EOSEQ ADC_ISR_EOS /* TODO - keep only one? */ +#define ADC_ISR_EOC (1 << 2) +#define ADC_ISR_EOSMP (1 << 1) +#define ADC_ISR_ADRDY (1 << 0) + +/* ADC_IER Values -----------------------------------------------------------*/ + +/* AWD1IE: Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD1IE (1 << 7) +/* OVRIE: Overrun interrupt enable */ +#define ADC_IER_OVRIE (1 << 4) +/* EOSIE: End of regular sequence of conversions interrupt enable */ +#define ADC_IER_EOSIE (1 << 3) +#define ADC_IER_EOSEQIE ADC_IER_EOSIE /* TODO - keep only one? */ +/* EOCIE: End of regular conversion interrupt enable */ +#define ADC_IER_EOCIE (1 << 2) +/* EOSMPIE: End of sampling flag interrupt enable for regular conversions */ +#define ADC_IER_EOSMPIE (1 << 1) +/* ADRDYIE : ADC ready interrupt enable */ +#define ADC_IER_ADRDYIE (1 << 0) + +/* ADC_CR Values -----------------------------------------------------------*/ + +/* ADCAL: ADC calibration */ +#define ADC_CR_ADCAL (1 << 31) +/* ADSTP: ADC stop of regular conversion command */ +#define ADC_CR_ADSTP (1 << 4) +/* ADSTART: ADC start of regular conversion */ +#define ADC_CR_ADSTART (1 << 2) +/* ADDIS: ADC disable command */ +#define ADC_CR_ADDIS (1 << 1) +/* ADEN: ADC enable control */ +#define ADC_CR_ADEN (1 << 0) + +/* ADC_CFGR1 Values -----------------------------------------------------------*/ + +/* AWD1CH[4:0]: Analog watchdog 1 channel selection */ +#define ADC_CFGR1_AWD1CH_SHIFT 26 +#define ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT) +#define ADC_CFGR1_AWD1CH_VAL(x) ((x) << ADC_CFGR1_AWD1CH_SHIFT) + +/* AWD1EN: Analog watchdog 1 enable on regular channels */ +#define ADC_CFGR1_AWD1EN (1 << 23) + +/* AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1SGL (1 << 22) + +/* DISCEN: Discontinuous mode for regular channels */ +#define ADC_CFGR1_DISCEN (1 << 16) + +/* AUTDLY: Delayed conversion mode */ +#define ADC_CFGR1_AUTDLY (1 << 14) + +/* CONT: Single / continuous conversion mode for regular conversions */ +#define ADC_CFGR1_CONT (1 << 13) + +/* OVRMOD: Overrun Mode */ +#define ADC_CFGR1_OVRMOD (1 << 12) + +/* + * EXTEN[1:0]: External trigger enable and polarity selection for regular + * channels + */ +#define ADC_CFGR1_EXTEN_DISABLED (0x0 << 10) +#define ADC_CFGR1_EXTEN_RISING_EDGE (0x1 << 10) +#define ADC_CFGR1_EXTEN_FALLING_EDGE (0x2 << 10) +#define ADC_CFGR1_EXTEN_BOTH_EDGES (0x3 << 10) + +#define ADC_CFGR1_EXTEN_MASK (0x3 << 10) + +/* ALIGN: Data alignment */ +#define ADC_CFGR1_ALIGN (1 << 5) + +/* RES[1:0]: Data resolution */ +#define ADC_CFGR1_RES_12_BIT (0x0 << 3) +#define ADC_CFGR1_RES_10_BIT (0x1 << 3) +#define ADC_CFGR1_RES_8_BIT (0x2 << 3) +#define ADC_CFGR1_RES_6_BIT (0x3 << 3) +#define ADC_CFGR1_RES_MASK (0x3 << 3) + +/* DMACFG: Direct memory access configuration */ +#define ADC_CFGR1_DMACFG (1 << 1) + +/* DMAEN: Direct memory access enable */ +#define ADC_CFGR1_DMAEN (1 << 0) + +/* ADC_TR1 Values ------------------------------------------------------------*/ + +#define ADC_TR1_LT_SHIFT 0 +#define ADC_TR1_LT (0xFFF << ADC_TR1_LT_SHIFT) +#define ADC_TR1_LT_VAL(x) ((x) << ADC_TR1_LT_SHIFT) + +#define ADC_TR1_HT_SHIFT 16 +#define ADC_TR1_HT (0xFFF << ADC_TR1_HT_SHIFT) +#define ADC_TR1_HT_VAL(x) ((x) << ADC_TR1_HT_SHIFT) + + /* ADC_CCR Values -----------------------------------------------------------*/ #define ADC_CCR_VBATEN (1 << 24) diff --git a/include/libopencm3/stm32/common/adc_common_v2_multi.h b/include/libopencm3/stm32/common/adc_common_v2_multi.h new file mode 100644 index 00000000..fb630415 --- /dev/null +++ b/include/libopencm3/stm32/common/adc_common_v2_multi.h @@ -0,0 +1,156 @@ +/** @addtogroup adc_defines + +@author @htmlonly © @endhtmlonly 2015 Karl Palsson + + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H +The order of header inclusion is important. adc.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_ADC_H +/** @endcond */ +#ifndef LIBOPENCM3_ADC_COMMON_V2_MULTI_H +#define LIBOPENCM3_ADC_COMMON_V2_MULTI_H + +/* + * The adc v2 peripheral optionally supports per channel sampling, injected + * sequences, watchdogs, offsets and other "advanced" features, and is + * found on the (so far) F3 and L4, + * or only a much "simpler" version as found on (so far) f0 and l0. + */ + +/* ----- ADC registers -----------------------------------------------------*/ +/* Sample Time Register 2 */ +#define ADC_SMPR2(adc) MMIO32((adc) + 0x18) +/* Watchdog Threshold Register 2 */ +#define ADC_TR2(adc) MMIO32((adc) + 0x24) +/* Watchdog Threshold Register 3 */ +#define ADC_TR3(adc) MMIO32((adc) + 0x28) +/* Regular Sequence Register x (ADCx_SQRy, x=1..4, y=1..4) SQRy */ +#define ADC_SQR1(adc) MMIO32((adc) + 0x30) +#define ADC_SQR2(adc) MMIO32((adc) + 0x34) +#define ADC_SQR3(adc) MMIO32((adc) + 0x38) +#define ADC_SQR4(adc) MMIO32((adc) + 0x3C) + +/* Injected Sequence Register (ADCx_JSQR, x=1..4) JSQR */ +#define ADC_JSQR(adc) MMIO32((adc) + 0x30) + +/* Offset Register x (ADCx_OFRy, x=1..4) (y=1..4) OFRy */ +#define ADC_OFR1(adc) MMIO32((adc) + 0x60) +#define ADC_OFR2(adc) MMIO32((adc) + 0x64) +#define ADC_OFR3(adc) MMIO32((adc) + 0x68) +#define ADC_OFR4(adc) MMIO32((adc) + 0x6C) + +/* Injected Data Register y (ADCx_JDRy, x=1..4, y= 1..4) JDRy */ +#define ADC_JDR1(adc) MMIO32((adc) + 0x80) +#define ADC_JDR2(adc) MMIO32((adc) + 0x84) +#define ADC_JDR3(adc) MMIO32((adc) + 0x88) +#define ADC_JDR4(adc) MMIO32((adc) + 0x8C) + +/* Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..4) AWD2CR */ +#define ADC_AWD2CR(adc) MMIO32((adc) + 0xA0) +/* Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..4) AWD3CR */ +#define ADC_AWD3CR(adc) MMIO32((adc) + 0xA4) + +/* Differential Mode Selection Register 2 (ADCx_DIFSEL, x=1..4) DIFSEL */ +#define ADC_DIFSEL(adc) MMIO32((adc) + 0xB0) + +/* Calibration Factors (ADCx_CALFACT, x=1..4) CALFACT */ +#define ADC_CALFACT(adc) MMIO32((adc) + 0xB4) + +/* ADC common (shared) registers */ +#define ADC_CSR(adc) MMIO32((adc) + 0x300 + 0x0) +#define ADC_CDR(adc) MMIO32((adc) + 0x300 + 0xa) + +/* --- Register values ------------------------------------------------------*/ +/* ADC_ISR Values -----------------------------------------------------------*/ + +/* QOVF: Injected context queue overflow */ +#define ADC_ISR_JQOVF (1 << 10) +/* AWD3: Analog watchdog 3 flag */ +#define ADC_ISR_AWD3 (1 << 9) +/* AWD2: Analog watchdog 2 flag */ +#define ADC_ISR_AWD2 (1 << 8) +/* JEOS: Injected channel end of sequence flag */ +#define ADC_ISR_JEOS (1 << 6) +/* JEOC: Injected channel end of conversion flag */ +#define ADC_ISR_JEOC (1 << 5) + +/* ADC_IER Values -----------------------------------------------------------*/ + +/* JQOVFIE: Injected context queue overflow interrupt enable */ +#define ADC_IER_JQOVFIE (1 << 10) +/* AWD3IE: Analog watchdog 3 interrupt enable */ +#define ADC_IER_AWD3IE (1 << 9) +/* AWD2IE: Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD2IE (1 << 8) +/* JEOSIE: End of injected sequence of conversions interrupt enable */ +#define ADC_IER_JEOSIE (1 << 6) +/* JEOCIE: End of injected conversion interrupt enable */ +#define ADC_IER_JEOCIE (1 << 5) + +/* ADC_CR Values ------------------------------------------------------------*/ + +/* ADCALDIF: Differential mode for calibration */ +#define ADC_CR_ADCALDIF (1 << 30) +/* JADSTP: ADC stop of injected conversion command */ +#define ADC_CR_JADSTP (1 << 5) +/* JADSTART: ADC start of injected conversion */ +#define ADC_CR_JADSTART (1 << 3) + +/* ADC_CFGR1 Values ---------------------------------------------------------*/ + +/* JAUTO: Autoamtic injected group conversion */ +#define ADC_CFGR1_JAUTO (1 << 25) + +/* JAWD1EN: Analog watchdog 1 enable on injected channels */ +#define ADC_CFGR1_JAWD1EN (1 << 24) + +/* JQM: JSQR queue mode */ +#define ADC_CFGR1_JQM (1 << 21) + +/* JDISCEN: Discontinuous mode on injected channels */ +#define ADC_CFGR1_JDISCEN (1 << 20) + +/* DISCNUM[2:0]: Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_SHIFT 17 +#define ADC_CFGR1_DISCNUM_MASK (0x7 << ADC_CFGR1_DISCNUM_SHIFT) +#define ADC_CFGR1_DISCNUM_VAL(x) (((x) - 1) << ADC_CFGR1_DISCNUM_SHIFT) + +/* EXTSEL[3:0]: External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_SHIFT 6 +#define ADC_CFGR1_EXTSEL_MASK (0xf << ADC_CFGR1_EXTSEL_SHIFT) +#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +END_DECLS + +#endif +#endif /* LIBOPENCM3_ADC_H */ +/**@}*/ diff --git a/include/libopencm3/stm32/common/adc_common_v2_single.h b/include/libopencm3/stm32/common/adc_common_v2_single.h new file mode 100644 index 00000000..59d2b32e --- /dev/null +++ b/include/libopencm3/stm32/common/adc_common_v2_single.h @@ -0,0 +1,72 @@ +/** @addtogroup adc_defines + +@author @htmlonly © @endhtmlonly 2015 Karl Palsson + + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H +The order of header inclusion is important. adc.h includes the device +specific memorymap.h header before including this header file.*/ + +/* + * The adc v2 peripheral optionally supports per channel sampling, injected + * sequences, watchdogs, offsets and other "advanced" features, and is + * found on the (so far) F3 and L4, + * or only a much "simpler" version as found on (so far) f0 and l0. + */ + +/** @cond */ +#ifdef LIBOPENCM3_ADC_H +/** @endcond */ +#ifndef LIBOPENCM3_ADC_COMMON_V2_SINGLE_H +#define LIBOPENCM3_ADC_COMMON_V2_SINGLE_H + +/* ----- ADC registers -----------------------------------------------------*/ +/* Channel Select Register */ +#define ADC_CHSELR(adc) MMIO32((adc) + 0x28) + +/* ----- ADC registers values -----------------------------------------------*/ +/* ADC_CFGR1 values */ +#define ADC_CFGR1_WAIT (1<<14) +/* EXTSEL[2:0]: External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_SHIFT 6 +#define ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT) +#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT) + +#define ADC_CFGR1_SCANDIR (1 << 2) + +/* ADC_CHSELR Values --------------------------------------------------------*/ + +#define ADC_CHSELR_CHSEL(x) (1 << (x)) + + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +END_DECLS + +#endif +#endif /* LIBOPENCM3_ADC_H */ +/**@}*/ diff --git a/include/libopencm3/stm32/f0/adc.h b/include/libopencm3/stm32/f0/adc.h index d86ea236..b1c43a0b 100644 --- a/include/libopencm3/stm32/f0/adc.h +++ b/include/libopencm3/stm32/f0/adc.h @@ -34,6 +34,7 @@ #define LIBOPENCM3_ADC_H #include +#include /*****************************************************************************/ /* Module definitions */ @@ -51,116 +52,24 @@ /* Register definitions */ /*****************************************************************************/ -/* ADC interrupt and status register */ -#define ADC_ISR(base) MMIO32((base) + 0x00) #define ADC1_ISR ADC_ISR(ADC) - -/* Interrupt Enable Register */ -#define ADC_IER(base) MMIO32((base) + 0x04) #define ADC1_IER ADC_IER(ADC) - -/* Control Register */ -#define ADC_CR(base) MMIO32((base) + 0x08) #define ADC1_CR ADC_CR(ADC) - - -/* Configuration Register 1 */ -#define ADC_CFGR1(base) MMIO32((base) + 0x0C) #define ADC1_CFGR1 ADC_CFGR1(ADC) - - -/* Configuration Register 2 */ -#define ADC_CFGR2(base) MMIO32((base) + 0x10) #define ADC1_CFGR2 ADC_CFGR2(ADC) - - -/* Sample Time Register 1 */ -#define ADC_SMPR(base) MMIO32((base) + 0x14) -#define ADC1_SMPR ADC_SMPR(ADC) - - -/* Watchdog Threshold Register */ -#define ADC_TR(base) MMIO32((base) + 0x20) -#define ADC1_TR ADC_TR(ADC) - - -/* Channel Select Register */ -#define ADC_CHSELR(base) MMIO32((base) + 0x28) +#define ADC1_SMPR1 ADC_SMPR1(ADC) +#define ADC_SMPR(adc) ADC_SMPR1(adc) /* Compatibility */ +#define ADC1_SMPR ADC_SMPR1(ADC) /* Compatibility */ +#define ADC1_TR1 ADC_TR1(ADC) +#define ADC_TR(adc) ADC_TR1(adc) /* Compatibility */ +#define ADC1_TR ADC1_TR(ADC) /* Compatibility */ #define ADC1_CHSELR ADC_CHSELR(ADC) - - -/* Regular Data Register */ -#define ADC_DR(base) MMIO32((base) + 0x40) #define ADC1_DR ADC_DR(ADC) /*****************************************************************************/ /* Register values */ /*****************************************************************************/ -/* ADC_ISR Values -----------------------------------------------------------*/ - -#define ADC_ISR_AWD (1 << 7) -#define ADC_ISR_OVR (1 << 4) -#define ADC_ISR_EOSEQ (1 << 3) -#define ADC_ISR_EOC (1 << 2) -#define ADC_ISR_EOSMP (1 << 1) -#define ADC_ISR_ADRDY (1 << 0) - -/* ADC_IER Values -----------------------------------------------------------*/ - -#define ADC_IER_AWDIE (1 << 7) -#define ADC_IER_OVRIE (1 << 4) -#define ADC_IER_EOSEQIE (1 << 3) -#define ADC_IER_EOCIE (1 << 2) -#define ADC_IER_EOSMPIE (1 << 1) -#define ADC_IER_ADRDYIE (1 << 0) - -/* ADC_CR Values ------------------------------------------------------------*/ - -#define ADC_CR_ADCAL (1 << 31) -#define ADC_CR_ADSTP (1 << 4) -#define ADC_CR_ADSTART (1 << 2) -#define ADC_CR_ADDIS (1 << 1) -#define ADC_CR_ADEN (1 << 0) - -/* ADC_CFGR1 Values ---------------------------------------------------------*/ - -#define ADC_CFGR1_AWDCH_SHIFT 26 -#define ADC_CFGR1_AWDCH (0x1F << ADC_CFGR1_AWDCH_SHIFT) -#define ADC_CFGR1_AWDCH_VAL(x) ((x) << ADC_CFGR1_AWDCH_SHIFT) - -#define ADC_CFGR1_AWDEN (1 << 23) -#define ADC_CFGR1_AWDSGL (1 << 22) -#define ADC_CFGR1_DISCEN (1 << 16) -#define ADC_CFGR1_AUTOFF (1 << 15) -#define ADC_CFGR1_WAIT (1 << 14) -#define ADC_CFGR1_CONT (1 << 13) -#define ADC_CFGR1_OVRMOD (1 << 12) - -#define ADC_CFGR1_EXTEN_SHIFT 10 -#define ADC_CFGR1_EXTEN (3 << ADC_CFGR1_EXTEN_SHIFT) -#define ADC_CFGR1_EXTEN_DISABLE (0 << ADC_CFGR1_EXTEN_SHIFT) -#define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) -#define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) -#define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) - -#define ADC_CFGR1_EXTSEL_SHIFT 6 -#define ADC_CFGR1_EXTSEL (7 << ADC_CFGR1_EXTSEL_SHIFT) -#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT) - -#define ADC_CFGR1_ALIGN (1 << 5) - -#define ADC_CFGR1_RES_SHIFT 3 -#define ADC_CFGR1_RES (3 << ADC_CFGR1_RES_SHIFT) -#define ADC_CFGR1_RES_12_BIT (0 << ADC_CFGR1_RES_SHIFT) -#define ADC_CFGR1_RES_10_BIT (1 << ADC_CFGR1_RES_SHIFT) -#define ADC_CFGR1_RES_8_BIT (2 << ADC_CFGR1_RES_SHIFT) -#define ADC_CFGR1_RES_6_BIT (3 << ADC_CFGR1_RES_SHIFT) - -#define ADC_CFGR1_SCANDIR (1 << 2) -#define ADC_CFGR1_DMACFG (1 << 1) -#define ADC_CFGR1_DMAEN (1 << 0) - /* ADC_CFGR2 Values ---------------------------------------------------------*/ #define ADC_CFGR2_CKMODE_SHIFT 30 @@ -182,24 +91,6 @@ #define ADC_SMPR_SMP_071DOT5 (6 << ADC_SMPR_SMP_SHIFT) #define ADC_SMPR_SMP_239DOT5 (7 << ADC_SMPR_SMP_SHIFT) -/* ADC_TR Values ------------------------------------------------------------*/ - -#define ADC_TR_LT_SHIFT 0 -#define ADC_TR_LT (0xFFF << ADC_TR_LT_SHIFT) -#define ADC_TR_LT_VAL(x) ((x) << ADC_TR_LT_SHIFT) - -#define ADC_TR_HT_SHIFT 16 -#define ADC_TR_HT (0xFFF << ADC_TR_HT_SHIFT) -#define ADC_TR_HT_VAL(x) ((x) << ADC_TR_HT_SHIFT) - -/* ADC_CHSELR Values --------------------------------------------------------*/ - -#define ADC_CHSELR_CHSEL(x) (1 << (x)) - -/* ADC_DR Values ------------------------------------------------------------*/ - -#define ADC_DR_DATA 0xFFFF - /*****************************************************************************/ /* API definitions */ diff --git a/include/libopencm3/stm32/f3/adc.h b/include/libopencm3/stm32/f3/adc.h index 4bd8fa20..9e363d87 100644 --- a/include/libopencm3/stm32/f3/adc.h +++ b/include/libopencm3/stm32/f3/adc.h @@ -35,6 +35,7 @@ #define LIBOPENCM3_ADC_H #include +#include #define ADC1 ADC1_BASE #define ADC2 ADC2_BASE @@ -46,32 +47,21 @@ /*----------- ADC registers -------------------------------------- */ -/* ADC interrupt and status register (ADCx_ISR, x=1..4) */ -#define ADC_ISR(adc_base) MMIO32((adc_base) + 0x00) #define ADC1_ISR ADC_ISR(ADC1_BASE) #define ADC2_ISR ADC_ISR(ADC2_BASE) #define ADC3_ISR ADC_ISR(ADC3_BASE) #define ADC4_ISR ADC_ISR(ADC4_BASE) - -/* Interrupt Enable Register (ADCx_IER, x=1..4) IER */ -#define ADC_IER(adc_base) MMIO32((adc_base) + 0x04) #define ADC1_IER ADC_IER(ADC1_BASE) #define ADC2_IER ADC_IER(ADC2_BASE) #define ADC3_IER ADC_IER(ADC3_BASE) #define ADC4_IER ADC_IER(ADC4_BASE) - -/* Control Register (ADCx_CR, x=1..4) CR */ -#define ADC_CR(adc_base) MMIO32((adc_base) + 0x08) #define ADC1_CR ADC_CR(ADC1_BASE) #define ADC2_CR ADC_CR(ADC2_BASE) #define ADC3_CR ADC_CR(ADC3_BASE) #define ADC4_CR ADC_CR(ADC4_BASE) - -/* Configuration Register (ADCx_CFGR1, x=1..4) CFGR */ -#define ADC_CFGR1(adc_base) MMIO32((adc_base) + 0x0C) #define ADC1_CFGR1 ADC_CFGR1(ADC1_BASE) #define ADC2_CFGR1 ADC_CFGR1(ADC2_BASE) #define ADC3_CFGR1 ADC_CFGR1(ADC3_BASE) @@ -83,173 +73,116 @@ #define ADC3_CFGR ADC_CFGR1(ADC3_BASE) #define ADC4_CFGR ADC_CFGR1(ADC4_BASE) - -/* Sample Time Register 1 (ADCx_SMPR1, x=1..4) SMPR1 */ -#define ADC_SMPR1(adc_base) MMIO32((adc_base) + 0x14) #define ADC1_SMPR1 ADC_SMPR1(ADC1_BASE) #define ADC2_SMPR1 ADC_SMPR1(ADC2_BASE) #define ADC3_SMPR1 ADC_SMPR1(ADC3_BASE) #define ADC4_SMPR1 ADC_SMPR1(ADC4_BASE) - -/* Sample Time Register 2 (ADCx_SMPR2, x=1..4) SMPR2 */ -#define ADC_SMPR2(adc_base) MMIO32((adc_base) + 0x18) #define ADC1_SMPR2 ADC_SMPR2(ADC1_BASE) #define ADC2_SMPR2 ADC_SMPR2(ADC2_BASE) #define ADC3_SMPR2 ADC_SMPR2(ADC3_BASE) #define ADC4_SMPR2 ADC_SMPR2(ADC4_BASE) - -/* Watchdog Threshold Register 1 (ADCx_TR1, x=1..4) TR1 */ -#define ADC_TR1(adc_base) MMIO32((adc_base) + 0x20) #define ADC1_TR1 ADC_TR1(ADC1_BASE) #define ADC2_TR1 ADC_TR1(ADC2_BASE) #define ADC3_TR1 ADC_TR1(ADC3_BASE) #define ADC4_TR1 ADC_TR1(ADC4_BASE) - -/* Watchdog Threshold Register 2 (ADCx_TR2, x=1..4) TR2 */ -#define ADC_TR2(adc_base) MMIO32((adc_base) + 0x24) #define ADC1_TR2 ADC_TR2(ADC1_BASE) #define ADC2_TR2 ADC_TR2(ADC2_BASE) #define ADC3_TR2 ADC_TR2(ADC3_BASE) #define ADC4_TR2 ADC_TR2(ADC4_BASE) - -/* Watchdog Threshold Register 3 (ADCx_TR3, x=1..4) TR3 */ -#define ADC_TR3(adc_base) MMIO32((adc_base) + 0x28) #define ADC1_TR3 ADC_TR3(ADC1_BASE) #define ADC2_TR3 ADC_TR3(ADC2_BASE) #define ADC3_TR3 ADC_TR3(ADC3_BASE) #define ADC4_TR3 ADC_TR3(ADC4_BASE) - -/* Regular Sequence Register 1 (ADCx_SQR1, x=1..4) SQR1 */ -#define ADC_SQR1(adc_base) MMIO32((adc_base) + 0x30) #define ADC1_SQR1 ADC_SQR1(ADC1_BASE) #define ADC2_SQR1 ADC_SQR1(ADC2_BASE) #define ADC3_SQR1 ADC_SQR1(ADC3_BASE) #define ADC4_SQR1 ADC_SQR1(ADC4_BASE) - -/* Regular Sequence Register 2 (ADCx_SQR2, x=1..4) SQR2 */ -#define ADC_SQR2(adc_base) MMIO32((adc_base) + 0x34) #define ADC1_SQR2 ADC_SQR2(ADC1_BASE) #define ADC2_SQR2 ADC_SQR2(ADC2_BASE) #define ADC3_SQR2 ADC_SQR2(ADC3_BASE) #define ADC4_SQR2 ADC_SQR2(ADC4_BASE) - -/* Regular Sequence Register 3 (ADCx_SQR3, x=1..4) SQR3 */ -#define ADC_SQR3(adc_base) MMIO32((adc_base) + 0x38) #define ADC1_SQR3 ADC_SQR3(ADC1_BASE) #define ADC2_SQR3 ADC_SQR3(ADC2_BASE) #define ADC3_SQR3 ADC_SQR3(ADC3_BASE) #define ADC4_SQR3 ADC_SQR3(ADC4_BASE) - -/* Regular Sequence Register 4 (ADCx_SQR3, x=1..4) SQR4 */ -#define ADC_SQR4(adc_base) MMIO32((adc_base) + 0x3C) #define ADC1_SQR4 ADC_SQR4(ADC1_BASE) #define ADC2_SQR4 ADC_SQR4(ADC2_BASE) #define ADC3_SQR4 ADC_SQR4(ADC3_BASE) #define ADC4_SQR4 ADC_SQR4(ADC4_BASE) - -/* regular Data Register (ADCx_DR, x=1..4) DR */ -#define ADC_DR(adc_base) MMIO32((adc_base) + 0x40) #define ADC1_DR ADC_DR(ADC1_BASE) #define ADC2_DR ADC_DR(ADC2_BASE) #define ADC3_DR ADC_DR(ADC3_BASE) #define ADC4_DR ADC_DR(ADC4_BASE) - -/* Injected Sequence Register (ADCx_JSQR, x=1..4) JSQR */ -#define ADC_JSQR(adc_base) MMIO32((adc_base) + 0x30) #define ADC1_JSQR ADC_JSQR(ADC1_BASE) #define ADC2_JSQR ADC_JSQR(ADC2_BASE) #define ADC3_JSQR ADC_JSQR(ADC3_BASE) #define ADC4_JSQR ADC_JSQR(ADC4_BASE) - -/* Offset Register x (ADCx_OFRy, x=1..4) (y=1..4) OFRy */ -#define ADC_OFR1(adc_base) MMIO32((adc_base) + 0x60) #define ADC1_OFR1 ADC_OFR1(ADC1_BASE) #define ADC2_OFR1 ADC_OFR1(ADC2_BASE) #define ADC3_OFR1 ADC_OFR1(ADC3_BASE) #define ADC4_OFR1 ADC_OFR1(ADC4_BASE) -#define ADC_OFR2(adc_base) MMIO32((adc_base) + 0x64) #define ADC1_OFR2 ADC_OFR2(ADC1_BASE) #define ADC2_OFR2 ADC_OFR2(ADC2_BASE) #define ADC3_OFR2 ADC_OFR2(ADC3_BASE) #define ADC4_OFR2 ADC_OFR2(ADC4_BASE) -#define ADC_OFR3(adc_base) MMIO32((adc_base) + 0x68) #define ADC1_OFR3 ADC_OFR3(ADC1_BASE) #define ADC2_OFR3 ADC_OFR3(ADC2_BASE) #define ADC3_OFR3 ADC_OFR3(ADC3_BASE) #define ADC4_OFR3 ADC_OFR3(ADC4_BASE) -#define ADC_OFR4(adc_base) MMIO32((adc_base) + 0x6C) #define ADC1_OFR4 ADC_OFR4(ADC1_BASE) #define ADC2_OFR4 ADC_OFR4(ADC2_BASE) #define ADC3_OFR4 ADC_OFR4(ADC3_BASE) #define ADC4_OFR4 ADC_OFR4(ADC4_BASE) - -/* Injected Data Register y (ADCx_JDRy, x=1..4, y= 1..4) JDRy */ -#define ADC_JDR1(adc_base) MMIO32((adc_base) + 0x80) #define ADC1_JDR1 ADC_JDR1(ADC1_BASE) #define ADC2_JDR1 ADC_JDR1(ADC2_BASE) #define ADC3_JDR1 ADC_JDR1(ADC3_BASE) #define ADC4_JDR1 ADC_JDR1(ADC4_BASE) -#define ADC_JDR2(adc_base) MMIO32((adc_base) + 0x84) #define ADC1_JDR2 ADC_JDR2(ADC1_BASE) #define ADC2_JDR2 ADC_JDR2(ADC2_BASE) #define ADC3_JDR2 ADC_JDR2(ADC3_BASE) #define ADC4_JDR2 ADC_JDR2(ADC4_BASE) -#define ADC_JDR3(adc_base) MMIO32((adc_base) + 0x88) #define ADC1_JDR3 ADC_JDR3(ADC1_BASE) #define ADC2_JDR3 ADC_JDR3(ADC2_BASE) #define ADC3_JDR3 ADC_JDR3(ADC3_BASE) #define ADC4_JDR3 ADC_JDR3(ADC4_BASE) -#define ADC_JDR4(adc_base) MMIO32((adc_base) + 0x8C) #define ADC1_JDR4 ADC_JDR4(ADC1_BASE) #define ADC2_JDR4 ADC_JDR4(ADC2_BASE) #define ADC3_JDR4 ADC_JDR4(ADC3_BASE) #define ADC4_JDR4 ADC_JDR4(ADC4_BASE) - -/* Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..4) AWD2CR */ -#define ADC_AWD2CR(adc_base) MMIO32((adc_base) + 0xA0) #define ADC1_AWD2CR ADC_AWD2CR(ADC1_BASE) #define ADC2_AWD2CR ADC_AWD2CR(ADC2_BASE) #define ADC3_AWD2CR ADC_AWD2CR(ADC3_BASE) #define ADC4_AWD2CR ADC_AWD2CR(ADC4_BASE) - -/* Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..4) AWD3CR */ -#define ADC_AWD3CR(adc_base) MMIO32((adc_base) + 0xA4) #define ADC1_AWD3CR ADC_AWD3CR(ADC1_BASE) #define ADC2_AWD3CR ADC_AWD3CR(ADC2_BASE) #define ADC3_AWD3CR ADC_AWD3CR(ADC3_BASE) #define ADC4_AWD3CR ADC_AWD3CR(ADC4_BASE) - -/* Differential Mode Selection Register 2 (ADCx_DIFSEL, x=1..4) DIFSEL */ -#define ADC_DIFSEL(adc_base) MMIO32((adc_base) + 0xB0) #define ADC1_DIFSEL ADC_DIFSEL(ADC1_BASE) #define ADC2_DIFSEL ADC_DIFSEL(ADC2_BASE) #define ADC3_DIFSEL ADC_DIFSEL(ADC3_BASE) #define ADC4_DIFSEL ADC_DIFSEL(ADC4_BASE) - -/* Calibration Factors (ADCx_CALFACT, x=1..4) CALFACT */ -#define ADC_CALFACT(adc_base) MMIO32((adc_base) + 0xB4) #define ADC1_CALFACT ADC_CALFACT(ADC1_BASE) #define ADC2_CALFACT ADC_CALFACT(ADC2_BASE) #define ADC3_CALFACT ADC_CALFACT(ADC3_BASE) @@ -263,226 +196,13 @@ #define ADC34_CDR ADC_CDR(ADC3) -/*------- ADC_ISR values ---------*/ - -/* QOVF: Injected context queue overflow */ -#define ADC_ISR_JQOVF (1 << 10) - -/* AWD3: Analog watchdog 3 flag */ -#define ADC_ISR_AWD3 (1 << 9) - -/* AWD2: Analog watchdog 2 flag */ -#define ADC_ISR_AWD2 (1 << 8) - -/* AWD1: Analog watchdog 1 flag */ -#define ADC_ISR_AWD1 (1 << 7) - -/* JEOS: Injected channel end of sequence flag */ -#define ADC_ISR_JEOS (1 << 6) - -/* JEOC: Injected channel end of conversion flag */ -#define ADC_ISR_JEOC (1 << 5) - -/* OVR: ADC overrun */ -#define ADC_ISR_OVR (1 << 4) - -/* EOS: End of regular sequence flag */ -#define ADC_ISR_EOS (1 << 3) - -/* EOC: End of conversion flag */ -#define ADC_ISR_EOC (1 << 2) - -/* EOSMP: End of sampling flag */ -#define ADC_ISR_EOSMP (1 << 1) - -/* ADRDY: ADC ready */ -#define ADC_ISR_ADRDY (1 << 0) - - -/*------- ADC_IER values ---------*/ - -/* JQOVFIE: Injected context queue overflow interrupt enable */ -#define ADC_IER_JQOVFIE (1 << 10) - -/* AWD3IE: Analog watchdog 3 interrupt enable */ -#define ADC_IER_AWD3IE (1 << 9) - -/* AWD2IE: Analog watchdog 2 interrupt enable */ -#define ADC_IER_AWD2IE (1 << 8) - -/* AWD1IE: Analog watchdog 1 interrupt enable */ -#define ADC_IER_AWD1IE (1 << 7) - -/* JEOSIE: End of injected sequence of conversions interrupt enable */ -#define ADC_IER_JEOSIE (1 << 6) - -/* JEOCIE: End of injected conversion interrupt enable */ -#define ADC_IER_JEOCIE (1 << 5) - -/* OVRIE: Overrun interrupt enable */ -#define ADC_IER_OVRIE (1 << 4) - -/* EOSIE: End of regular sequence of conversions interrupt enable */ -#define ADC_IER_EOSIE (1 << 3) - -/* EOCIE: End of regular conversion interrupt enable */ -#define ADC_IER_EOCIE (1 << 2) - -/* EOSMPIE: End of sampling flag interrupt enable for regular conversions */ -#define ADC_IER_EOSMPIE (1 << 1) - -/* ADRDYIE : ADC ready interrupt enable */ -#define ADC_IER_ADRDYIE (1 << 0) - - /*------- ADC_CR values ---------*/ -/* ADCAL: ADC calibration */ -#define ADC_CR_ADCAL (1 << 31) - -/* ADCALDIF: Differential mode for calibration */ -#define ADC_CR_ADCALDIF (1 << 30) - /** ADVREGEN: ADC voltage regulator enable */ #define ADC_CR_ADVREGEN_ENABLE (0x1 << 28) #define ADC_CR_ADVREGEN_DISABLE (0x2 << 28) #define ADC_CR_ADVREGEN_MASK (0x3 << 28) -/* JADSTP: ADC stop of injected conversion command */ -#define ADC_CR_JADSTP (1 << 5) - -/* ADSTP: ADC stop of regular conversion command */ -#define ADC_CR_ADSTP (1 << 4) - -/* JADSTART: ADC start of injected conversion */ -#define ADC_CR_JADSTART (1 << 3) - -/* ADSTART: ADC start of regular conversion */ -#define ADC_CR_ADSTART (1 << 2) - -/* ADDIS: ADC disable command */ -#define ADC_CR_ADDIS (1 << 1) - -/* ADEN: ADC enable control */ -#define ADC_CR_ADEN (1 << 0) - - -/*------- ADC_CFGR1 values ---------*/ - -/* AWD1CH[4:0]: Analog watchdog 1 channel selection */ -/* Bit 0x0 reserved */ -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_1 (0x01 << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_2 (0x02 << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_3 (0x03 << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_4 (0x04 << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_5 (0x05 << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_6 (0x06 << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_7 (0x07 << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_8 (0x08 << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_9 (0x09 << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_10 (0x0A << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_11 (0x0B << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_12 (0x0C << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_13 (0x0D << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_14 (0x0E << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_15 (0x0F << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_16 (0x10 << 26) -#define ADC_CFGR1_AWD1CH_ADC_IN_CH_17 (0x11 << 26) - -#define ADC_CFGR1_AWD1CH_MASK (0x1F << 26) - -/* Ohters bits reserved, must not be used */ - -/* JAUTO: Autoamtic injected group conversion */ -#define ADC_CFGR1_JAUTO (1 << 25) - -/* JAWD1EN: Analog watchdog 1 enable on injected channels */ -#define ADC_CFGR1_JAWD1EN (1 << 24) - -/* AWD1EN: Analog watchdog 1 enable on regular channels */ -#define ADC_CFGR1_AWD1EN (1 << 23) - -/* AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */ -#define ADC_CFGR1_AWD1SGL (1 << 22) - -/* JQM: JSQR queue mode */ -#define ADC_CFGR1_JQM (1 << 21) - -/* JDISCEN: Discontinuous mode on injected channels */ -#define ADC_CFGR1_JDISCEN (1 << 20) - -/* DISCNUM[2:0]: Discontinuous mode channel count */ -#define ADC_CFGR1_DISCNUM_1_CH (0x0 << 17) -#define ADC_CFGR1_DISCNUM_2_CH (0x1 << 17) -#define ADC_CFGR1_DISCNUM_3_CH (0x2 << 17) -#define ADC_CFGR1_DISCNUM_4_CH (0x3 << 17) -#define ADC_CFGR1_DISCNUM_5_CH (0x4 << 17) -#define ADC_CFGR1_DISCNUM_6_CH (0x5 << 17) -#define ADC_CFGR1_DISCNUM_7_CH (0x6 << 17) -#define ADC_CFGR1_DISCNUM_8_CH (0x7 << 17) -#define ADC_CFGR1_DISCNUM_SHIFT 17 - -/* DISCEN: Discontinuous mode for regular channels */ -#define ADC_CFGR1_DISCEN (1 << 16) - -/* AUTDLY: Delayed conversion mode */ -#define ADC_CFGR1_AUTDLY (1 << 14) - -/* CONT: Single / continuous conversion mode for regular conversions */ -#define ADC_CFGR1_CONT (1 << 13) - -/* OVRMOD: Overrun Mode */ -#define ADC_CFGR1_OVRMOD (1 << 12) - -/* - * EXTEN[1:0]: External trigger enable and polarity selection for regular - * channels - */ -#define ADC_CFGR1_EXTEN_DISABLED (0x0 << 10) -#define ADC_CFGR1_EXTEN_RISING_EDGE (0x1 << 10) -#define ADC_CFGR1_EXTEN_FALLING_EDGE (0x2 << 10) -#define ADC_CFGR1_EXTEN_BOTH_EDGES (0x3 << 10) - -#define ADC_CFGR1_EXTEN_MASK (0x3 << 10) - -/* EXTSEL[3:0]: External trigger selection for regular group */ -#define ADC_CFGR1_EXTSEL_EVENT_0 (0x0 << 6) -#define ADC_CFGR1_EXTSEL_EVENT_1 (0x1 << 6) -#define ADC_CFGR1_EXTSEL_EVENT_2 (0x2 << 6) -#define ADC_CFGR1_EXTSEL_EVENT_3 (0x3 << 6) -#define ADC_CFGR1_EXTSEL_EVENT_4 (0x4 << 6) -#define ADC_CFGR1_EXTSEL_EVENT_5 (0x5 << 6) -#define ADC_CFGR1_EXTSEL_EVENT_6 (0x6 << 6) -#define ADC_CFGR1_EXTSEL_EVENT_7 (0x7 << 6) -#define ADC_CFGR1_EXTSEL_EVENT_8 (0x8 << 6) -#define ADC_CFGR1_EXTSEL_EVENT_9 (0x9 << 6) -#define ADC_CFGR1_EXTSEL_EVENT_10 (0xA << 6) -#define ADC_CFGR1_EXTSEL_EVENT_11 (0xB << 6) -#define ADC_CFGR1_EXTSEL_EVENT_12 (0xC << 6) -#define ADC_CFGR1_EXTSEL_EVENT_13 (0xD << 6) -#define ADC_CFGR1_EXTSEL_EVENT_14 (0xE << 6) -#define ADC_CFGR1_EXTSEL_EVENT_15 (0xF << 6) - -#define ADC_CFGR1_EXTSEL_MASK (0xF << 6) - -/* ALIGN: Data alignment */ -#define ADC_CFGR1_ALIGN (1 << 5) - -/* RES[1:0]: Data resolution */ -#define ADC_CFGR1_RES_12_BIT (0x0 << 3) -#define ADC_CFGR1_RES_10_BIT (0x1 << 3) -#define ADC_CFGR1_RES_8_BIT (0x2 << 3) -#define ADC_CFGR1_RES_6_BIT (0x3 << 3) - -#define ADC_CFGR1_RES_MASK (0x3 << 3) - -/* DMACFG: Direct memory access configuration */ -#define ADC_CFGR1_DMACFG (1 << 1) - -/* DMAEN: Direct memory access enable */ -#define ADC_CFGR1_DMAEN (1 << 0) - - /****************************************************************************/ /* ADC_SMPRx ADC Sample Time Selection for Channels */ /** @defgroup adc_sample ADC Sample Time Selection values @@ -501,13 +221,6 @@ /* SMPx[2:0]: Channel x sampling time selection */ -/*------- ADC_TR1 values ---------*/ - -/* Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold */ - -/* Bit 11:0 LT1[11:0]: Analog watchdog 1 lower threshold */ - - /*------- ADC_T2 values ---------*/ /* Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold */ diff --git a/lib/stm32/f0/adc.c b/lib/stm32/f0/adc.c index 64c3dd67..a34fe25b 100644 --- a/lib/stm32/f0/adc.c +++ b/lib/stm32/f0/adc.c @@ -233,7 +233,7 @@ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity) { ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_EXTSEL) | trigger; - ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_EXTEN) | polarity; + ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_EXTEN_MASK) | polarity; } /*---------------------------------------------------------------------------*/ @@ -244,7 +244,7 @@ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, void adc_disable_external_trigger_regular(uint32_t adc) { - ADC_CFGR1(adc) &= ~ADC_CFGR1_EXTEN; + ADC_CFGR1(adc) &= ~ADC_CFGR1_EXTEN_MASK; } /**@}*/ @@ -268,7 +268,7 @@ void adc_disable_external_trigger_regular(uint32_t adc) void adc_enable_watchdog_interrupt(uint32_t adc) { - ADC_IER(adc) |= ADC_IER_AWDIE; + ADC_IER(adc) |= ADC_IER_AWD1IE; } /*---------------------------------------------------------------------------*/ @@ -279,7 +279,7 @@ void adc_enable_watchdog_interrupt(uint32_t adc) void adc_disable_watchdog_interrupt(uint32_t adc) { - ADC_IER(adc) &= ~ADC_IER_AWDIE; + ADC_IER(adc) &= ~ADC_IER_AWD1IE; } /*---------------------------------------------------------------------------*/ @@ -294,7 +294,7 @@ void adc_disable_watchdog_interrupt(uint32_t adc) bool adc_get_watchdog_flag(uint32_t adc) { - return ADC_ISR(adc) & ADC_ISR_AWD; + return ADC_ISR(adc) & ADC_ISR_AWD1; } /*---------------------------------------------------------------------------*/ @@ -305,7 +305,7 @@ bool adc_get_watchdog_flag(uint32_t adc) void adc_clear_watchdog_flag(uint32_t adc) { - ADC_ISR(adc) = ADC_ISR_AWD; + ADC_ISR(adc) = ADC_ISR_AWD1; } /*---------------------------------------------------------------------------*/ @@ -524,7 +524,7 @@ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) void adc_set_resolution(uint32_t adc, uint16_t resolution) { - ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_RES) | resolution; + ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_RES_MASK) | resolution; } /*---------------------------------------------------------------------------*/ @@ -673,8 +673,8 @@ void adc_calibrate_wait_finish(uint32_t adc) void adc_enable_analog_watchdog_on_all_channels(uint32_t adc) { - ADC_CFGR1(adc) |= ADC_CFGR1_AWDEN; - ADC_CFGR1(adc) &= ~ADC_CFGR1_AWDSGL; + ADC_CFGR1(adc) |= ADC_CFGR1_AWD1EN; + ADC_CFGR1(adc) &= ~ADC_CFGR1_AWD1SGL; } /*---------------------------------------------------------------------------*/ @@ -686,10 +686,10 @@ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc) void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan) { - ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) | - ADC_CFGR1_AWDCH_VAL(chan); + ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWD1CH) | + ADC_CFGR1_AWD1CH_VAL(chan); - ADC_CFGR1(adc) |= ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL; + ADC_CFGR1(adc) |= ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL; } /*---------------------------------------------------------------------------*/ @@ -699,7 +699,7 @@ void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan) */ void adc_disable_analog_watchdog(uint32_t adc) { - ADC_CFGR1(adc) &= ~ADC_CFGR1_AWDEN; + ADC_CFGR1(adc) &= ~ADC_CFGR1_AWD1EN; } /*---------------------------------------------------------------------------*/ @@ -711,7 +711,7 @@ void adc_disable_analog_watchdog(uint32_t adc) void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold) { - ADC_TR(adc) = (ADC_TR(adc) & ~ADC_TR_HT) | ADC_TR_HT_VAL(threshold); + ADC_TR1(adc) = (ADC_TR1(adc) & ~ADC_TR1_HT) | ADC_TR1_HT_VAL(threshold); } /*---------------------------------------------------------------------------*/ @@ -723,7 +723,7 @@ void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold) void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold) { - ADC_TR(adc) = (ADC_TR(adc) & ~ADC_TR_LT) | ADC_TR_LT_VAL(threshold); + ADC_TR1(adc) = (ADC_TR1(adc) & ~ADC_TR1_LT) | ADC_TR1_LT_VAL(threshold); } /**@}*/ diff --git a/lib/stm32/f3/adc.c b/lib/stm32/f3/adc.c index a07877b1..39408532 100644 --- a/lib/stm32/f3/adc.c +++ b/lib/stm32/f3/adc.c @@ -287,7 +287,7 @@ void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, { uint32_t reg32; - reg32 = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWD1CH_MASK); /* Clear bit [4:0]. */ + reg32 = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWD1CH); /* Clear bit [4:0]. */ if (channel < 18) { reg32 |= channel; }