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stm32g0: lptim: add additional cr bits and cfgr2 reg.

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This commit is contained in:
Guillaume Revaillot 2019-07-03 17:19:48 +02:00
parent 811aebf096
commit f99e711873
1 changed files with 23 additions and 0 deletions
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23
include/libopencm3/stm32/g0/lptimer.h
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@ -39,6 +39,29 @@
#define LPTIM2 LPTIM2_BASE
/**@}*/
/** LPTIM_CFGR2 LPTIM configuration register 2 */
#define LPTIM_CFGR2(tim_base) MMIO32((tim_base) + 0x24)
/** @addtogroup lptim_cr
@{*/
/** COUNTRST Counter reset **/
#define LPTIM_CR_COUNTRST (1 << 3)
/** RSTARE Reset after read enable **/
#define LPTIM_CR_RSTARE (1 << 4)
/**@}*/
/** @defgroup lptim_cfgr2 LPTIM_CFGR2 Configuration Register 2
@{*/
#define LPTIM_CFGR2_IN2SEL_SHIFT 4
#define LPTIM_CFGR2_IN2SEL_MASK 0x03
#define LPTIM_CFGR2_IN1SEL_SHIFT 0
#define LPTIM_CFGR2_IN1SEL_MASK 0x03
/**@}*/
BEGIN_DECLS
END_DECLS