stm32:usart-v2: pull out registers and values
Only pulling out the _common_ stuff. This is a single step in a long process of eliminating all the duplication and "same, but different" implementations that are stalling adding nice clean easy support for l0/f7/l4. This _ignores_ all currently conflict register definitions, even if they "do the same thing" it just pulls up the common stuff. A subsequent commit can look at resolving the implementatations to a single version.
This commit is contained in:
Karl Palsson
parent
668c7c5079
commit
fb520ff3dc
@ -28,22 +28,520 @@
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#ifndef LIBOPENCM3_USART_COMMON_V2_H
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#define LIBOPENCM3_USART_COMMON_V2_H
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/** @defgroup usart_registers USART Registers
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@ingroup usart_defines
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@{*/
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/** Control register 1 (USARTx_CR1) */
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#define USART_CR1(usart_base) MMIO32((usart_base) + 0x00)
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#define USART1_CR1 USART_CR1(USART1_BASE)
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#define USART2_CR1 USART_CR1(USART2_BASE)
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#define USART3_CR1 USART_CR1(USART3_BASE)
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#if defined(USART4_BASE)
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#define USART4_CR1 USART_CR1(USART4_BASE)
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#endif
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#if defined(UART4_BASE)
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#define UART4_CR1 USART_CR1(UART4_BASE)
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#endif
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#if defined(UART5_BASE)
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#define UART5_CR1 USART_CR1(UART5_BASE)
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#endif
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/** Control register 2 (USARTx_CR2) */
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#define USART_CR2(usart_base) MMIO32((usart_base) + 0x04)
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#define USART1_CR2 USART_CR2(USART1_BASE)
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#define USART2_CR2 USART_CR2(USART2_BASE)
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#define USART3_CR2 USART_CR2(USART3_BASE)
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#if defined(USART4_BASE)
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#define USART4_CR2 USART_CR2(USART4_BASE)
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#endif
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#if defined(UART4_BASE)
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#define UART4_CR2 USART_CR2(UART4_BASE)
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#endif
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#if defined(UART5_BASE)
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#define UART5_CR2 USART_CR2(UART5_BASE)
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#endif
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/** Control register 3 (USARTx_CR3) */
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#define USART_CR3(usart_base) MMIO32((usart_base) + 0x08)
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#define USART1_CR3 USART_CR3(USART1_BASE)
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#define USART2_CR3 USART_CR3(USART2_BASE)
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#define USART3_CR3 USART_CR3(USART3_BASE)
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#if defined(USART4_BASE)
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#define USART4_CR3 USART_CR3(USART4_BASE)
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#endif
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#if defined(UART4_BASE)
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#define UART4_CR3 USART_CR3(UART4_BASE)
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#endif
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#if defined(UART5_BASE)
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#define UART5_CR3 USART_CR3(UART5_BASE)
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#endif
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/** Baud rate register (USARTx_BRR) */
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#define USART_BRR(usart_base) MMIO32((usart_base) + 0x0C)
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#define USART1_BRR USART_BRR(USART1_BASE)
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#define USART2_BRR USART_BRR(USART2_BASE)
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#define USART3_BRR USART_BRR(USART3_BASE)
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#if defined(USART4_BASE)
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#define USART4_BRR USART_BRR(USART4_BASE)
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#endif
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#if defined(UART4_BASE)
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#define UART4_BRR USART_BRR(UART4_BASE)
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#endif
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#if defined(UART5_BASE)
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#define UART5_BRR USART_BRR(UART5_BASE)
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#endif
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/** Guard time and prescaler register (USARTx_GTPR) */
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#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x10)
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#define USART1_GTPR USART_GTPR(USART1_BASE)
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#define USART2_GTPR USART_GTPR(USART2_BASE)
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#define USART3_GTPR USART_GTPR(USART3_BASE)
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#if defined(USART4_BASE)
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#define USART4_GTPR USART_GTPR(USART4_BASE)
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#endif
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#if defined(UART4_BASE)
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#define UART4_GTPR USART_GTPR(UART4_BASE)
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#endif
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#if defined(UART5_BASE)
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#define UART5_GTPR USART_GTPR(UART5_BASE)
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#endif
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/** Receiver timeout register (USART_RTOR) */
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#define USART_RTOR(usart_base) MMIO32((usart_base) + 0x14)
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#define USART1_RTOR USART_RTOR(USART1_BASE)
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#define USART2_RTOR USART_RTOR(USART2_BASE)
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#define USART3_RTOR USART_RTOR(USART3_BASE)
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#if defined(USART4_BASE)
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#define USART4_RTOR USART_RTOR(USART4_BASE)
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#endif
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#if defined(UART4_BASE)
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#define UART4_RTOR USART_RTOR(UART4_BASE)
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#endif
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#if defined(UART5_BASE)
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#define UART5_RTOR USART_RTOR(UART5_BASE)
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#endif
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/** Request register (USART_RQR) */
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#define USART_RQR(usart_base) MMIO32((usart_base) + 0x18)
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#define USART1_RQR USART_RQR(USART1_BASE)
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#define USART2_RQR USART_RQR(USART2_BASE)
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#define USART3_RQR USART_RQR(USART3_BASE)
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#if defined(USART4_BASE)
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#define USART4_RQR USART_RQR(USART4_BASE)
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#endif
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#if defined(UART4_BASE)
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#define UART4_RQR USART_RQR(UART4_BASE)
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#endif
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#if defined(UART5_BASE)
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#define UART5_RQR USART_RQR(UART5_BASE)
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#endif
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/** Interrupt & status register (USART_ISR) */
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#define USART_ISR(usart_base) MMIO32((usart_base) + 0x1C)
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#define USART1_ISR USART_ISR(USART1_BASE)
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#define USART2_ISR USART_ISR(USART2_BASE)
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#define USART3_ISR USART_ISR(USART3_BASE)
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#if defined(USART4_BASE)
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#define USART4_ISR USART_ISR(USART4_BASE)
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#endif
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#if defined(UART4_BASE)
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#define UART4_ISR USART_ISR(UART4_BASE)
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#endif
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#if defined(UART5_BASE)
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#define UART5_ISR USART_ISR(UART5_BASE)
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#endif
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/** Interrupt flag clear register (USART_ICR) */
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#define USART_ICR(usart_base) MMIO32((usart_base) + 0x20)
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#define USART1_ICR USART_ICR(USART1_BASE)
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#define USART2_ICR USART_ICR(USART2_BASE)
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#define USART3_ICR USART_ICR(USART3_BASE)
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#if defined(USART4_BASE)
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#define USART4_ICR USART_ICR(USART4_BASE)
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#endif
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#if defined(UART4_BASE)
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#define UART4_ICR USART_ICR(UART4_BASE)
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#endif
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#if defined(UART5_BASE)
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#define UART5_ICR USART_ICR(UART5_BASE)
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#endif
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/** Receive data register (USART_RDR) */
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#define USART_RDR(usart_base) MMIO32((usart_base) + 0x24)
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#define USART1_RDR USART_RDR(USART1_BASE)
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#define USART2_RDR USART_RDR(USART2_BASE)
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#define USART3_RDR USART_RDR(USART3_BASE)
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#if defined(USART4_BASE)
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#define USART4_RDR USART_RDR(USART4_BASE)
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#endif
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#if defined(UART4_BASE)
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#define UART4_RDR USART_RDR(UART4_BASE)
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#endif
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#if defined(UART5_BASE)
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#define UART5_RDR USART_RDR(UART5_BASE)
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#endif
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/** Transmit data register (USART_TDR) */
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#define USART_TDR(usart_base) MMIO32((usart_base) + 0x28)
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#define USART1_TDR USART_TDR(USART1_BASE)
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#define USART2_TDR USART_TDR(USART2_BASE)
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#define USART3_TDR USART_TDR(USART3_BASE)
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#if defined(USART4_BASE)
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#define USART4_TDR USART_TDR(USART4_BASE)
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#endif
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#if defined(UART4_BASE)
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#define UART4_TDR USART_TDR(UART4_BASE)
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#endif
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#if defined(UART5_BASE)
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#define UART5_TDR USART_TDR(UART5_BASE)
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#endif
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/**@}*/
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/*****************************************************************************/
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/* Register values */
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/*****************************************************************************/
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/* --- USART_RTOR values --------------------------------------------------- */
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/** @defgroup usart_cr1_values USART_CR1 Values
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@ingroup usart_defines
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@{*/
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/* BLEN[7:0]: Block Length */
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/** M1: Wordlength. @sa M0 */
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#define USART_CR1_M1 (1 << 28) /* F07x */
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/** EOBIE: End of Block interrupt enable */
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#define USART_CR1_EOBIE (1 << 27)
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/** RTOIE: Receiver timeout interrupt enable */
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#define USART_CR1_RTOIE (1 << 26)
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/* DEAT[4:0]: Driver Enable assertion time */
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/* DEDT[4:0]: Driver Enable deassertion time */
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/** OVER8: Oversampling mode */
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#define USART_CR1_OVER8 (1 << 15)
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/** CMIE: Character match interrupt enable */
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#define USART_CR1_CMIE (1 << 14)
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/** MME: Mute mode enable */
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#define USART_CR1_MME (1 << 13)
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/** M0: Word length */
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#define USART_CR1_M0 (1 << 12)
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/** @deprecated alias for M0.*/
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#define USART_CR1_M USART_CR1_M0
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/** WAKE: Receiver wakeup method */
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#define USART_CR1_WAKE (1 << 11)
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/** PCE: Parity control enable */
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#define USART_CR1_PCE (1 << 10)
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/** PS: Parity selection */
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#define USART_CR1_PS (1 << 9)
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/** PEIE: PE interrupt enable */
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#define USART_CR1_PEIE (1 << 8)
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/** TXEIE: Interrupt enable */
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#define USART_CR1_TXEIE (1 << 7)
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/** TCIE: Transmission complete interrupt enable */
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#define USART_CR1_TCIE (1 << 6)
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/** RXNEIE: RXNE interrupt enable */
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#define USART_CR1_RXNEIE (1 << 5)
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/** IDLEIE: IDLE interrupt enable */
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#define USART_CR1_IDLEIE (1 << 4)
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/** TE: Transmitter enable */
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#define USART_CR1_TE (1 << 3)
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/** RE: Receiver enable */
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#define USART_CR1_RE (1 << 2)
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/** UESM: USART enable in Stop mode */
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#define USART_CR1_UESM (1 << 1)
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/** UE: USART enable */
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#define USART_CR1_UE (1 << 0)
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/**@}*/
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/*------------------------------------------------*/
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/** @defgroup usart_cr2_values USART_CR2 Values
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@ingroup usart_defines
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@{*/
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/** RTOEN: Receiver timeout enable */
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#define USART_CR2_RTOEN (1 << 23)
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/** ABREN: Auto baud rate enable */
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#define USART_CR2_ABREN (1 << 20)
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/** MSBFIRST: Most significant bit first */
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#define USART_CR2_MSBFIRST (1 << 19)
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/** DATAINV: Binary data inversion */
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#define USART_CR2_DATAINV (1 << 18)
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/** TXINV: TX pin active level inversion */
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#define USART_CR2_TXINV (1 << 17)
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/** RXINV: RX pin active level inversion */
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#define USART_CR2_RXINV (1 << 16)
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/** SWAP: Swap TX/RX pins */
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#define USART_CR2_SWAP (1 << 15)
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/** LINEN: LIN mode enable */
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#define USART_CR2_LINEN (1 << 14)
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/** CLKEN: Clock enable */
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#define USART_CR2_CLKEN (1 << 11)
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/** CPOL: Clock polarity */
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#define USART_CR2_CPOL (1 << 10)
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/** CPHA: Clock phase */
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#define USART_CR2_CPHA (1 << 9)
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/** LBCL: Last bit clock pulse */
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#define USART_CR2_LBCL (1 << 8)
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/** LBDIE: LIN break detection interrupt enable */
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#define USART_CR2_LBDIE (1 << 6)
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/** LBDL: LIN break detection length */
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#define USART_CR2_LBDL (1 << 5)
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/** ADDM7:7-bit Address Detection/4-bit Address Detection */
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#define USART_CR2_ADDM7 (1 << 4)
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/**@}*/
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/*------------------------------------------------*/
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/** @defgroup usart_cr3_values USART_CR3 Values
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@ingroup usart_defines
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@{*/
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/** WUFIE: Wakeup from Stop mode interrupt enable */
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#define USART_CR3_WUFIE (1 << 22)
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/** WUS[1:0]: Wakeup from Stop mode interrupt flag selection */
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#define USART_CR3_WUS_ADDRMATCH (0x0 << 20)
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#define USART_CR3_WUS_START_BIT (0x2 << 20)
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#define USART_CR3_WUS_RXNE (0x3 << 20)
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/** DEP: Driver enable polarity selection */
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#define USART_CR3_DEP (1 << 15)
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/** DEM: Driver enable mode */
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#define USART_CR3_DEM (1 << 14)
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/** DDRE: DMA Disable on Reception Error */
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#define USART_CR3_DDRE (1 << 13)
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/** OVRDIS: Overrun Disable */
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#define USART_CR3_OVRDIS (1 << 12)
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/** ONEBIT: One sample bit method enable */
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#define USART_CR3_ONEBIT (1 << 11)
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/** CTSIE: CTS interrupt enable. Not on UARTs */
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#define USART_CR3_CTSIE (1 << 10)
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/** CTSE: CTS enable. Not on UARTS */
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#define USART_CR3_CTSE (1 << 9)
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/** RTSE: RTS enable. Not on UARTs */
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#define USART_CR3_RTSE (1 << 8)
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/** DMAT: DMA enable transmitter. Not on UARTs */
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#define USART_CR3_DMAT (1 << 7)
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/** DMAR: DMA enable receiver. Not on UARTS */
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#define USART_CR3_DMAR (1 << 6)
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/** SCEN: Smartcard mode enable. Not on UARTs */
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#define USART_CR3_SCEN (1 << 5)
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/** NACK: Smartcard NACK enable. Not UARTs */
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#define USART_CR3_NACK (1 << 4)
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/** HDSEL: Half-duplex selection */
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#define USART_CR3_HDSEL (1 << 3)
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/** IRLP: IrDA low-power */
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#define USART_CR3_IRLP (1 << 2)
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/** IREN: IrDA mode enable */
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#define USART_CR3_IREN (1 << 1)
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/** EIE: Error interrupt enable */
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#define USART_CR3_EIE (1 << 0)
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/**@}*/
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/* ------------------------------------------------------ */
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/** @defgroup usart_rtor_values USART_RTOR Values
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* @ingroup usart_defines
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* @{
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*/
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/** BLEN[7:0]: Block Length */
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#define USART_RTOR_BLEN_SHIFT 24
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#define USART_RTOR_BLEN_MASK (0xFF << USART_RTOR_BLEN_SHIFT)
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#define USART_RTOR_BLEN_VAL(x) ((x) << USART_RTOR_BLEN_SHIFT)
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/* RTO[23:0]: Receiver timeout value */
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/** RTO[23:0]: Receiver timeout value */
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#define USART_RTOR_RTO_SHIFT 0
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#define USART_RTOR_RTO_MASK (0xFFFFF << USART_RTOR_RTO_SHIFT)
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#define USART_RTOR_RTO_VAL(x) ((x) << USART_RTOR_RTO_SHIFT)
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/**@}*/
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/* ------------------------------------------------------ */
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/** @defgroup usart_rqr_values USART_RQR Values
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* @ingroup usart_defines
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* @{
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*/
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/** TXFRQ: Transmit data flush request */
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#define USART_RQR_TXFRQ (1 << 4)
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/** RXFRQ: Receive data flush request */
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#define USART_RQR_RXFRQ (1 << 3)
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/** MMRQ: Mute mode request */
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#define USART_RQR_MMRQ (1 << 2)
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/** SBKRQ: Send break request */
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#define USART_RQR_SBKRQ (1 << 1)
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/** ABRRQ: Auto baud rate request */
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#define USART_RQR_ABKRQ (1 << 0)
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/**@}*/
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/* ------------------------------------------------------ */
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/** @defgroup usart_isr_values USART_ISR Values
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* @ingroup usart_defines
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* @{
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*/
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/** REACK: Receive enable acknowledge flag */
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#define USART_ISR_REACK (1 << 22)
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/** TEACK: Transmit enable acknowledge flag */
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#define USART_ISR_TEACK (1 << 21)
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/** WUF: Wakeup from Stop mode flag */
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#define USART_ISR_WUF (1 << 20)
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/** RWU: Receiver wakeup from Mute mode */
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#define USART_ISR_RWU (1 << 19)
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/** SBKF: Send break flag */
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#define USART_ISR_SBKF (1 << 18)
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/** CMF: Character match flag */
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#define USART_ISR_CMF (1 << 17)
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/** BUSY: Busy flag */
|
||||
#define USART_ISR_BUSY (1 << 16)
|
||||
|
||||
/** ABRF: Auto baud rate flag */
|
||||
#define USART_ISR_ABRF (1 << 15)
|
||||
|
||||
/** ABRE: Auto baud rate error */
|
||||
#define USART_ISR_ABRE (1 << 14)
|
||||
|
||||
/** EOBF: End of block flag */
|
||||
#define USART_ISR_EOBF (1 << 12)
|
||||
|
||||
/** RTOF: Receiver timeout */
|
||||
#define USART_ISR_RTOF (1 << 11)
|
||||
|
||||
/** CTS: CTS flag */
|
||||
#define USART_ISR_CTS (1 << 10)
|
||||
|
||||
/** CTSIF: CTS interrupt flag */
|
||||
#define USART_ISR_CTSIF (1 << 9)
|
||||
|
||||
/** LBDF: LIN break detection flag */
|
||||
#define USART_ISR_LBDF (1 << 8)
|
||||
|
||||
/** TXE: Transmit data register empty */
|
||||
#define USART_ISR_TXE (1 << 7)
|
||||
|
||||
/** TC: Transmission complete */
|
||||
#define USART_ISR_TC (1 << 6)
|
||||
|
||||
/** RXNE: Read data register not empty */
|
||||
#define USART_ISR_RXNE (1 << 5)
|
||||
|
||||
/** IDLE: Idle line detected */
|
||||
#define USART_ISR_IDLE (1 << 4)
|
||||
|
||||
/** ORE: Overrun error */
|
||||
#define USART_ISR_ORE (1 << 3)
|
||||
|
||||
/** NF: Noise detected flag */
|
||||
#define USART_ISR_NF (1 << 2)
|
||||
|
||||
/** FE: Framing error */
|
||||
#define USART_ISR_FE (1 << 1)
|
||||
|
||||
/** PE: Parity error */
|
||||
#define USART_ISR_PE (1 << 0)
|
||||
|
||||
/**@}*/
|
||||
|
||||
/* ------------------------------------------------------ */
|
||||
/** @defgroup usart_icr_values USART_ICR Values
|
||||
* @ingroup usart_defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** WUCF: Wakeup from Stop mode clear flag */
|
||||
#define USART_ICR_WUCF (1 << 20)
|
||||
|
||||
/** CMCF: Character match clear flag */
|
||||
#define USART_ICR_CMCF (1 << 17)
|
||||
|
||||
/** EOBCF: End of timeout clear flag */
|
||||
#define USART_ICR_EOBCF (1 << 12)
|
||||
|
||||
/** RTOCF: Receiver timeout clear flag */
|
||||
#define USART_ICR_RTOCF (1 << 11)
|
||||
|
||||
/** CTSCF: CTS clear flag */
|
||||
#define USART_ICR_CTSCF (1 << 9)
|
||||
|
||||
/** LBDCF: LIN break detection clear flag */
|
||||
#define USART_ICR_LBDCF (1 << 8)
|
||||
|
||||
/** TCCF: Transmission complete clear flag */
|
||||
#define USART_ICR_TCCF (1 << 6)
|
||||
|
||||
/** IDLECF: Idle line detected clear flag */
|
||||
#define USART_ICR_IDLECF (1 << 4)
|
||||
|
||||
/** ORECF: Overrun error clear flag */
|
||||
#define USART_ICR_ORECF (1 << 3)
|
||||
|
||||
/** NCF: Noise detected clear flag */
|
||||
#define USART_ICR_NCF (1 << 2)
|
||||
|
||||
/** FECF: Framing error clear flag */
|
||||
#define USART_ICR_FECF (1 << 1)
|
||||
|
||||
/** PECF: Parity error clear flag */
|
||||
#define USART_ICR_PECF (1 << 0)
|
||||
|
||||
/**@}*/
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
@ -42,86 +42,12 @@
|
||||
#define USART3 USART3_BASE
|
||||
#define USART4 USART4_BASE
|
||||
|
||||
/*****************************************************************************/
|
||||
/* Register definitions */
|
||||
/*****************************************************************************/
|
||||
|
||||
#define USART_CR1(usart_base) MMIO32((usart_base) + 0x00)
|
||||
#define USART1_CR1 USART_CR1(USART1_BASE)
|
||||
#define USART2_CR1 USART_CR1(USART2_BASE)
|
||||
#define USART3_CR1 USART_CR1(USART3_BASE)
|
||||
#define USART4_CR1 USART_CR1(USART4_BASE)
|
||||
|
||||
#define USART_CR2(usart_base) MMIO32((usart_base) + 0x04)
|
||||
#define USART1_CR2 USART_CR2(USART1_BASE)
|
||||
#define USART2_CR2 USART_CR2(USART2_BASE)
|
||||
#define USART3_CR2 USART_CR2(USART3_BASE)
|
||||
#define USART4_CR2 USART_CR2(USART4_BASE)
|
||||
|
||||
#define USART_CR3(usart_base) MMIO32((usart_base) + 0x08)
|
||||
#define USART1_CR3 USART_CR3(USART1_BASE)
|
||||
#define USART2_CR3 USART_CR3(USART2_BASE)
|
||||
#define USART3_CR3 USART_CR3(USART3_BASE)
|
||||
#define USART4_CR3 USART_CR3(USART4_BASE)
|
||||
|
||||
#define USART_BRR(usart_base) MMIO32((usart_base) + 0x0c)
|
||||
#define USART1_BRR USART_BRR(USART1_BASE)
|
||||
#define USART2_BRR USART_BRR(USART2_BASE)
|
||||
#define USART3_BRR USART_BRR(USART3_BASE)
|
||||
#define USART4_BRR USART_BRR(USART4_BASE)
|
||||
|
||||
#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x10)
|
||||
#define USART1_GTPR USART_GTPR(USART1_BASE)
|
||||
#define USART2_GTPR USART_GTPR(USART2_BASE)
|
||||
#define USART3_GTPR USART_GTPR(USART3_BASE)
|
||||
#define USART4_GTPR USART_GTPR(USART4_BASE)
|
||||
|
||||
#define USART_RTOR(usart_base) MMIO32((usart_base) + 0x14)
|
||||
#define USART1_RTOR USART_RTOR(USART1_BASE)
|
||||
#define USART2_RTOR USART_RTOR(USART2_BASE)
|
||||
#define USART3_RTOR USART_RTOR(USART3_BASE)
|
||||
#define USART4_RTOR USART_RTOR(USART4_BASE)
|
||||
|
||||
#define USART_RQR(usart_base) MMIO32((usart_base) + 0x18)
|
||||
#define USART1_RQR USART_RQR(USART1_BASE)
|
||||
#define USART2_RQR USART_RQR(USART2_BASE)
|
||||
#define USART3_RQR USART_RQR(USART3_BASE)
|
||||
#define USART4_RQR USART_RQR(USART4_BASE)
|
||||
|
||||
#define USART_ISR(usart_base) MMIO32((usart_base) + 0x1c)
|
||||
#define USART1_ISR USART_ISR(USART1_BASE)
|
||||
#define USART2_ISR USART_ISR(USART2_BASE)
|
||||
#define USART3_ISR USART_ISR(USART3_BASE)
|
||||
#define USART4_ISR USART_ISR(USART4_BASE)
|
||||
|
||||
#define USART_ICR(usart_base) MMIO32((usart_base) + 0x20)
|
||||
#define USART1_ICR USART_ICR(USART1_BASE)
|
||||
#define USART2_ICR USART_ICR(USART2_BASE)
|
||||
#define USART3_ICR USART_ICR(USART3_BASE)
|
||||
#define USART4_ICR USART_ICR(USART4_BASE)
|
||||
|
||||
#define USART_RDR(usart_base) MMIO16((usart_base) + 0x24)
|
||||
#define USART1_RDR USART_RDR(USART1_BASE)
|
||||
#define USART2_RDR USART_RDR(USART2_BASE)
|
||||
#define USART3_RDR USART_RDR(USART3_BASE)
|
||||
#define USART4_RDR USART_RDR(USART4_BASE)
|
||||
|
||||
#define USART_TDR(usart_base) MMIO16((usart_base) + 0x28)
|
||||
#define USART1_TDR USART_TDR(USART1_BASE)
|
||||
#define USART2_TDR USART_TDR(USART2_BASE)
|
||||
#define USART3_TDR USART_TDR(USART3_BASE)
|
||||
#define USART4_TDR USART_TDR(USART4_BASE)
|
||||
|
||||
/*****************************************************************************/
|
||||
/* Register values */
|
||||
/*****************************************************************************/
|
||||
|
||||
/* USART_CR1 Values ---------------------------------------------------------*/
|
||||
|
||||
#define USART_CR1_M1 (1 << 28) /* F07x */
|
||||
#define USART_CR1_EOBIE (1 << 27)
|
||||
#define USART_CR1_RTOIE (1 << 26)
|
||||
|
||||
#define USART_CR1_DEAT_SHIFT 21
|
||||
#define USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT)
|
||||
#define USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT)
|
||||
@ -130,92 +56,30 @@
|
||||
#define USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT)
|
||||
#define USART_CR1_DEDT_VAL(x) ((x) << USART_CR1_DEDT_SHIFT)
|
||||
|
||||
#define USART_CR1_OVER8 (1 << 15)
|
||||
#define USART_CR1_CMIE (1 << 14)
|
||||
#define USART_CR1_MME (1 << 13)
|
||||
#define USART_CR1_M (1 << 12) /* Obsolete, please use M0 */
|
||||
#define USART_CR1_M0 (1 << 12)
|
||||
#define USART_CR1_WAKE (1 << 11)
|
||||
#define USART_CR1_PCE (1 << 10)
|
||||
#define USART_CR1_PS (1 << 9)
|
||||
#define USART_CR1_PEIE (1 << 8)
|
||||
#define USART_CR1_TXEIE (1 << 7)
|
||||
#define USART_CR1_TCIE (1 << 6)
|
||||
#define USART_CR1_RXNEIE (1 << 5)
|
||||
#define USART_CR1_IDLEIE (1 << 4)
|
||||
#define USART_CR1_TE (1 << 3)
|
||||
#define USART_CR1_RE (1 << 2)
|
||||
#define USART_CR1_UESM (1 << 1)
|
||||
#define USART_CR1_UE (1 << 0)
|
||||
|
||||
/* USART_CR2 Values ---------------------------------------------------------*/
|
||||
|
||||
#define USART_CR2_ADD_SHIFT 24
|
||||
#define USART_CR2_ADD (0xFF << USART_CR2_ADD_SHIFT)
|
||||
#define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)
|
||||
|
||||
#define USART_CR2_RTOEN (1 << 23)
|
||||
|
||||
#define USART_CR2_ABRMOD_SHIFT 21
|
||||
#define USART_CR2_ABRMOD (3 << USART_CR2_ABRMOD_SHIFT)
|
||||
#define USART_CR2_ABRMOD_STARTBIT (0 << USART_CR2_ABRMOD_SHIFT)
|
||||
#define USART_CR2_ABRMOD_FALLTOFALL (1 << USART_CR2_ABRMOD_SHIFT)
|
||||
|
||||
#define USART_CR2_ABREN (1 << 20)
|
||||
#define USART_CR2_MSBFIRST (1 << 19)
|
||||
#define USART_CR2_DATAINV (1 << 18)
|
||||
#define USART_CR2_TXINV (1 << 17)
|
||||
#define USART_CR2_RXINV (1 << 16)
|
||||
#define USART_CR2_SWAP (1 << 15)
|
||||
#define USART_CR2_LINEN (1 << 14)
|
||||
|
||||
#define USART_CR2_STOP_SHIFT 12
|
||||
#define USART_CR2_STOP (3 << USART_CR2_STOP_SHIFT)
|
||||
#define USART_CR2_STOP_1_0BIT (0 << USART_CR2_STOP_SHIFT)
|
||||
#define USART_CR2_STOP_2_0BIT (2 << USART_CR2_STOP_SHIFT)
|
||||
#define USART_CR2_STOP_1_5BIT (3 << USART_CR2_STOP_SHIFT)
|
||||
|
||||
#define USART_CR2_CLKEN (1 << 11)
|
||||
#define USART_CR2_CPOL (1 << 10)
|
||||
#define USART_CR2_CPHA (1 << 9)
|
||||
#define USART_CR2_LBCL (1 << 8)
|
||||
#define USART_CR2_LBIDE (1 << 6)
|
||||
#define USART_CR2_LBDL (1 << 5)
|
||||
#define USART_CR2_ADDM (1 << 4) /* Obsolete, use ADDM7 */
|
||||
#define USART_CR2_ADDM7 (1 << 4)
|
||||
|
||||
/* USART_CR3 Values ---------------------------------------------------------*/
|
||||
|
||||
#define USART_CR3_WUFIE (1 << 22)
|
||||
|
||||
#define USART_CR3_WUS_SHIFT 20
|
||||
#define USART_CR3_WUS (3 << USART_CR3_WUS_SHIFT)
|
||||
#define USART_CR3_WUS_ADDRMATCH (0 << USART_CR3_WUS_SHIFT)
|
||||
#define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT)
|
||||
#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT)
|
||||
|
||||
#define USART_CR3_SCARCNT_SHIFT 17
|
||||
#define USART_CR3_SCARCNT (7 << USART_CR3_SCARCNT_SHIFT)
|
||||
#define USART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT)
|
||||
#define USART_CR3_SCARCNT_VAL(x) ((x) << USART_CR3_SCARCNT_SHIFT)
|
||||
|
||||
#define USART_CR3_DEP (1 << 15)
|
||||
#define USART_CR3_DEM (1 << 14)
|
||||
#define USART_CR3_DDRE (1 << 13)
|
||||
#define USART_CR3_OVRDIS (1 << 12)
|
||||
#define USART_CR3_ONEBIT (1 << 11)
|
||||
#define USART_CR3_CTSIE (1 << 10)
|
||||
#define USART_CR3_CTSE (1 << 9)
|
||||
#define USART_CR3_RTSE (1 << 8)
|
||||
#define USART_CR3_DMAT (1 << 7)
|
||||
#define USART_CR3_DMAR (1 << 6)
|
||||
#define USART_CR3_SCEN (1 << 5)
|
||||
#define USART_CR3_NACK (1 << 4)
|
||||
#define USART_CR3_HDSEL (1 << 3)
|
||||
#define USART_CR3_IRLP (1 << 2)
|
||||
#define USART_CR3_IREN (1 << 1)
|
||||
#define USART_CR3_EIE (1 << 0)
|
||||
|
||||
/* USART_GTPR Values --------------------------------------------------------*/
|
||||
|
||||
#define USART_GTPR_GT_SHIFT 8
|
||||
@ -226,54 +90,6 @@
|
||||
#define USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT)
|
||||
#define USART_GTPR_PSC_VAL(x) ((x) << USART_GTPR_PSC_SHIFT)
|
||||
|
||||
/* USART_RQR Values ---------------------------------------------------------*/
|
||||
|
||||
#define USART_RQR_TXFRQ (1 << 4)
|
||||
#define USART_RQR_RXFRQ (1 << 3)
|
||||
#define USART_RQR_MMRQ (1 << 2)
|
||||
#define USART_RQR_SBKRQ (1 << 1)
|
||||
#define USART_RQR_ABRRQ (1 << 0)
|
||||
|
||||
/* USART_ISR Values ---------------------------------------------------------*/
|
||||
|
||||
#define USART_ISR_REACK (1 << 22)
|
||||
#define USART_ISR_TEACK (1 << 21)
|
||||
#define USART_ISR_WUF (1 << 20)
|
||||
#define USART_ISR_RWU (1 << 19)
|
||||
#define USART_ISR_SBKF (1 << 18)
|
||||
#define USART_ISR_CMF (1 << 17)
|
||||
#define USART_ISR_BUSY (1 << 16)
|
||||
#define USART_ISR_ABRF (1 << 15)
|
||||
#define USART_ISR_ABRE (1 << 14)
|
||||
#define USART_ISR_EOBF (1 << 12)
|
||||
#define USART_ISR_RTOF (1 << 11)
|
||||
#define USART_ISR_CTS (1 << 10)
|
||||
#define USART_ISR_CTSIF (1 << 9)
|
||||
#define USART_ISR_LBDF (1 << 8)
|
||||
#define USART_ISR_TXE (1 << 7)
|
||||
#define USART_ISR_TC (1 << 6)
|
||||
#define USART_ISR_RXNE (1 << 5)
|
||||
#define USART_ISR_IDLE (1 << 4)
|
||||
#define USART_ISR_ORE (1 << 3)
|
||||
#define USART_ISR_NF (1 << 2)
|
||||
#define USART_ISR_FE (1 << 1)
|
||||
#define USART_ISR_PE (1 << 0)
|
||||
|
||||
/* USART_ICR Values ---------------------------------------------------------*/
|
||||
|
||||
#define USART_ICR_WUCF (1 << 20)
|
||||
#define USART_ICR_CMCF (1 << 17)
|
||||
#define USART_ICR_EOBCF (1 << 12)
|
||||
#define USART_ICR_RTOCF (1 << 11)
|
||||
#define USART_ICR_CTSCF (1 << 9)
|
||||
#define USART_ICR_LBDCF (1 << 8)
|
||||
#define USART_ICR_TCCF (1 << 6)
|
||||
#define USART_ICR_IDLECF (1 << 4)
|
||||
#define USART_ICR_ORECF (1 << 3)
|
||||
#define USART_ICR_NCF (1 << 2)
|
||||
#define USART_ICR_FECF (1 << 1)
|
||||
#define USART_ICR_PECF (1 << 0)
|
||||
|
||||
/*****************************************************************************/
|
||||
/* API definitions */
|
||||
/*****************************************************************************/
|
||||
|
||||
@ -34,156 +34,6 @@
|
||||
#include <libopencm3/stm32/common/usart_common_all.h>
|
||||
#include <libopencm3/stm32/common/usart_common_v2.h>
|
||||
|
||||
/* --- USART registers ----------------------------------------------------- */
|
||||
|
||||
/* Control register 1 (USARTx_CR1) */
|
||||
#define USART_CR1(usart_base) MMIO32((usart_base) + 0x00)
|
||||
#define USART1_CR1 USART_CR1(USART1_BASE)
|
||||
#define USART2_CR1 USART_CR1(USART2_BASE)
|
||||
#define USART3_CR1 USART_CR1(USART3_BASE)
|
||||
#define UART4_CR1 USART_CR1(UART4_BASE)
|
||||
#define UART5_CR1 USART_CR1(UART5_BASE)
|
||||
|
||||
/* Control register 2 (USARTx_CR2) */
|
||||
#define USART_CR2(usart_base) MMIO32((usart_base) + 0x04)
|
||||
#define USART1_CR2 USART_CR2(USART1_BASE)
|
||||
#define USART2_CR2 USART_CR2(USART2_BASE)
|
||||
#define USART3_CR2 USART_CR2(USART3_BASE)
|
||||
#define UART4_CR2 USART_CR2(UART4_BASE)
|
||||
#define UART5_CR2 USART_CR2(UART5_BASE)
|
||||
|
||||
/* Control register 3 (USARTx_CR3) */
|
||||
#define USART_CR3(usart_base) MMIO32((usart_base) + 0x08)
|
||||
#define USART1_CR3 USART_CR3(USART1_BASE)
|
||||
#define USART2_CR3 USART_CR3(USART2_BASE)
|
||||
#define USART3_CR3 USART_CR3(USART3_BASE)
|
||||
#define UART4_CR3 USART_CR3(UART4_BASE)
|
||||
#define UART5_CR3 USART_CR3(UART5_BASE)
|
||||
|
||||
/* Baud rate register (USARTx_BRR) */
|
||||
#define USART_BRR(usart_base) MMIO32((usart_base) + 0x0C)
|
||||
#define USART1_BRR USART_BRR(USART1_BASE)
|
||||
#define USART2_BRR USART_BRR(USART2_BASE)
|
||||
#define USART3_BRR USART_BRR(USART3_BASE)
|
||||
#define UART4_BRR USART_BRR(UART4_BASE)
|
||||
#define UART5_BRR USART_BRR(UART5_BASE)
|
||||
|
||||
/* Guard time and prescaler register (USARTx_GTPR) */
|
||||
#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x10)
|
||||
#define USART1_GTPR USART_GTPR(USART1_BASE)
|
||||
#define USART2_GTPR USART_GTPR(USART2_BASE)
|
||||
#define USART3_GTPR USART_GTPR(USART3_BASE)
|
||||
#define UART4_GTPR USART_GTPR(UART4_BASE)
|
||||
#define UART5_GTPR USART_GTPR(UART5_BASE)
|
||||
|
||||
/* Receiver timeout register (USART_RTOR) */
|
||||
#define USART_RTOR(usart_base) MMIO32((usart_base) + 0x14)
|
||||
#define USART1_RTOR USART_RTOR(USART1_BASE)
|
||||
#define USART2_RTOR USART_RTOR(USART2_BASE)
|
||||
#define USART3_RTOR USART_RTOR(USART3_BASE)
|
||||
#define UART4_RTOR USART_RTOR(UART4_BASE)
|
||||
#define UART5_RTOR USART_RTOR(UART5_BASE)
|
||||
|
||||
/* Request register (USART_RQR) */
|
||||
#define USART_RQR(usart_base) MMIO32((usart_base) + 0x18)
|
||||
#define USART1_RQR USART_RQR(USART1_BASE)
|
||||
#define USART2_RQR USART_RQR(USART2_BASE)
|
||||
#define USART3_RQR USART_RQR(USART3_BASE)
|
||||
#define UART4_RQR USART_RQR(UART4_BASE)
|
||||
#define UART5_RQR USART_RQR(UART5_BASE)
|
||||
|
||||
/* Interrupt & status register (USART_ISR) */
|
||||
#define USART_ISR(usart_base) MMIO32((usart_base) + 0x1C)
|
||||
#define USART1_ISR USART_ISR(USART1_BASE)
|
||||
#define USART2_ISR USART_ISR(USART2_BASE)
|
||||
#define USART3_ISR USART_ISR(USART3_BASE)
|
||||
#define UART4_ISR USART_ISR(UART4_BASE)
|
||||
#define UART5_ISR USART_ISR(UART5_BASE)
|
||||
|
||||
/* Interrupt flag clear register (USART_ICR) */
|
||||
#define USART_ICR(usart_base) MMIO32((usart_base) + 0x20)
|
||||
#define USART1_ICR USART_ICR(USART1_BASE)
|
||||
#define USART2_ICR USART_ICR(USART2_BASE)
|
||||
#define USART3_ICR USART_ICR(USART3_BASE)
|
||||
#define UART4_ICR USART_ICR(UART4_BASE)
|
||||
#define UART5_ICR USART_ICR(UART5_BASE)
|
||||
|
||||
/* Receive data register (USART_RDR) */
|
||||
#define USART_RDR(usart_base) MMIO32((usart_base) + 0x24)
|
||||
#define USART1_RDR USART_RDR(USART1_BASE)
|
||||
#define USART2_RDR USART_RDR(USART2_BASE)
|
||||
#define USART3_RDR USART_RDR(USART3_BASE)
|
||||
#define UART4_RDR USART_RDR(UART4_BASE)
|
||||
#define UART5_RDR USART_RDR(UART5_BASE)
|
||||
|
||||
/* Transmit data register (USART_TDR) */
|
||||
#define USART_TDR(usart_base) MMIO32((usart_base) + 0x28)
|
||||
#define USART1_TDR USART_TDR(USART1_BASE)
|
||||
#define USART2_TDR USART_TDR(USART2_BASE)
|
||||
#define USART3_TDR USART_TDR(USART3_BASE)
|
||||
#define UART4_TDR USART_TDR(UART4_BASE)
|
||||
#define UART5_TDR USART_TDR(UART5_BASE)
|
||||
|
||||
|
||||
/* --- USART_CR1 values ---------------------------------------------------- */
|
||||
|
||||
/* EOBIE: End of Block interrupt enable */
|
||||
#define USART_CR1_EOBIE (1 << 27)
|
||||
|
||||
/* RTOIE: Receiver timeout interrupt enable */
|
||||
#define USART_CR1_RTOIE (1 << 26)
|
||||
|
||||
/* DEAT[4:0]: Driver Enable assertion time */
|
||||
|
||||
/* DEDT[4:0]: Driver Enable deassertion time */
|
||||
|
||||
/* OVER8: Oversampling mode */
|
||||
#define USART_CR1_OVER8 (1 << 15)
|
||||
|
||||
/* CMIE: Character match interrupt enable */
|
||||
#define USART_CR1_CMIE (1 << 14)
|
||||
|
||||
/* MME: Mute mode enable */
|
||||
#define USART_CR1_MME (1 << 13)
|
||||
|
||||
/* M: Word length */
|
||||
#define USART_CR1_M (1 << 12)
|
||||
|
||||
/* WAKE: Receiver wakeup method */
|
||||
#define USART_CR1_WAKE (1 << 11)
|
||||
|
||||
/* PCE: Parity control enable */
|
||||
#define USART_CR1_PCE (1 << 10)
|
||||
|
||||
/* PS: Parity selection */
|
||||
#define USART_CR1_PS (1 << 9)
|
||||
|
||||
/* PEIE: PE interrupt enable */
|
||||
#define USART_CR1_PEIE (1 << 8)
|
||||
|
||||
/* TXEIE: Interrupt enable */
|
||||
#define USART_CR1_TXEIE (1 << 7)
|
||||
|
||||
/* TCIE: Transmission complete interrupt enable */
|
||||
#define USART_CR1_TCIE (1 << 6)
|
||||
|
||||
/* RXNEIE: RXNE interrupt enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5)
|
||||
|
||||
/* IDLEIE: IDLE interrupt enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4)
|
||||
|
||||
/* TE: Transmitter enable */
|
||||
#define USART_CR1_TE (1 << 3)
|
||||
|
||||
/* RE: Receiver enable */
|
||||
#define USART_CR1_RE (1 << 2)
|
||||
|
||||
/* UESM: USART enable in Stop mode */
|
||||
#define USART_CR1_UESM (1 << 1)
|
||||
|
||||
/* UE: USART enable */
|
||||
#define USART_CR1_UE (1 << 0)
|
||||
|
||||
|
||||
/* --- USART_CR2 values ---------------------------------------------------- */
|
||||
@ -194,36 +44,12 @@
|
||||
/* ADD[3:0]: Address of the USART node (27,24) */
|
||||
#define USART_CR2_ADD2_MASK (0xF << 24)
|
||||
|
||||
/* RTOEN: Receiver timeout enable */
|
||||
#define USART_CR2_RTOEN (1 << 23)
|
||||
|
||||
/* ABRMOD[1:0]: Auto baud rate mode */
|
||||
#define USART_CR2_ABRMOD_BAUD (0x0 << 21)
|
||||
#define USART_CR2_ABRMOD_FALL_EDGE (0x1 << 21)
|
||||
#define USART_CR2_ABRMOD_FRAME_0x7F (0x2 << 21)
|
||||
#define USART_CR2_ABRMOD_FRAME_0x55 (0x3 << 21)
|
||||
|
||||
/* ABREN: Auto baud rate enable */
|
||||
#define USART_CR2_ABREN (1 << 20)
|
||||
|
||||
/* MSBFIRST: Most significant bit first */
|
||||
#define USART_CR2_MSBFIRST (1 << 19)
|
||||
|
||||
/* DATAINV: Binary data inversion */
|
||||
#define USART_CR2_DATAINV (1 << 18)
|
||||
|
||||
/* TXINV: TX pin active level inversion */
|
||||
#define USART_CR2_TXINV (1 << 17)
|
||||
|
||||
/* RXINV: RX pin active level inversion */
|
||||
#define USART_CR2_RXINV (1 << 16)
|
||||
|
||||
/* SWAP: Swap TX/RX pins */
|
||||
#define USART_CR2_SWAP (1 << 15)
|
||||
|
||||
/* LINEN: LIN mode enable */
|
||||
#define USART_CR2_LINEN (1 << 14)
|
||||
|
||||
/* STOP[13:12]: STOP bits */
|
||||
#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */
|
||||
#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */
|
||||
@ -232,99 +58,16 @@
|
||||
#define USART_CR2_STOPBITS_MASK (0x03 << 12)
|
||||
#define USART_CR2_STOPBITS_SHIFT 12
|
||||
|
||||
/* CLKEN: Clock enable */
|
||||
#define USART_CR2_CLKEN (1 << 11)
|
||||
|
||||
/* CPOL: Clock polarity */
|
||||
#define USART_CR2_CPOL (1 << 10)
|
||||
|
||||
/* CPHA: Clock phase */
|
||||
#define USART_CR2_CPHA (1 << 9)
|
||||
|
||||
/* LBCL: Last bit clock pulse */
|
||||
#define USART_CR2_LBCL (1 << 8)
|
||||
|
||||
/* LBDIE: LIN break detection interrupt enable */
|
||||
#define USART_CR2_LBDIE (1 << 6)
|
||||
|
||||
/* LBDL: LIN break detection length */
|
||||
#define USART_CR2_LBDL (1 << 5)
|
||||
|
||||
/* ADDM7:7-bit Address Detection/4-bit Address Detection */
|
||||
#define USART_CR2_ADDM7 (1 << 4)
|
||||
|
||||
/* ADD[3:0]: Address of the usart node
|
||||
#define USART_CR2_ADD_MASK 0xF */
|
||||
|
||||
/* --- USART_CR3 values ---------------------------------------------------- */
|
||||
|
||||
/* WUFIE: Wakeup from Stop mode interrupt enable */
|
||||
#define USART_CR3_WUFIE (1 << 22)
|
||||
|
||||
/* WUS[1:0]: Wakeup from Stop mode interrupt flag selectio */
|
||||
#define USART_CR3_WUS_ON (0x0 << 20)
|
||||
/* RESERVE #define USART_CR3_WUS (0x1 << 20) */
|
||||
#define USART_CR3_WUS_START_BIT (0x2 << 20)
|
||||
#define USART_CR3_WUS_RXNE (0x3 << 20)
|
||||
|
||||
/* SCARCNT[2:0]: Smartcard auto-retry count */
|
||||
#define USART_CR3_SCARCNT_OFF (0x0 << 17)
|
||||
/* 0x1 to 0x7: number of automatic retransmission attempts */
|
||||
|
||||
/* DEP: Driver enable polarity selection */
|
||||
#define USART_CR3_DEP (1 << 15)
|
||||
|
||||
/* DEM: Driver enable mode */
|
||||
#define USART_CR3_DEM (1 << 14)
|
||||
|
||||
/* DDRE: DMA Disable on Reception Error */
|
||||
#define USART_CR3_DDRE (1 << 13)
|
||||
|
||||
/* OVRDIS: Overrun Disable */
|
||||
#define USART_CR3_OVRDIS (1 << 12)
|
||||
|
||||
/* ONEBIT: One sample bit method enable */
|
||||
#define USART_CR3_ONEBIT (1 << 11)
|
||||
|
||||
/* CTSIE: CTS interrupt enable */
|
||||
/* Note: N/A on UART4 & UART5 */
|
||||
#define USART_CR3_CTSIE (1 << 10)
|
||||
|
||||
/* CTSE: CTS enable */
|
||||
/* Note: N/A on UART4 & UART5 */
|
||||
#define USART_CR3_CTSE (1 << 9)
|
||||
|
||||
/* RTSE: RTS enable */
|
||||
/* Note: N/A on UART4 & UART5 */
|
||||
#define USART_CR3_RTSE (1 << 8)
|
||||
|
||||
/* DMAT: DMA enable transmitter */
|
||||
/* Note: N/A on UART5 */
|
||||
#define USART_CR3_DMAT (1 << 7)
|
||||
|
||||
/* DMAR: DMA enable receiver */
|
||||
/* Note: N/A on UART5 */
|
||||
#define USART_CR3_DMAR (1 << 6)
|
||||
|
||||
/* SCEN: Smartcard mode enable */
|
||||
/* Note: N/A on UART4 & UART5 */
|
||||
#define USART_CR3_SCEN (1 << 5)
|
||||
|
||||
/* NACK: Smartcard NACK enable */
|
||||
/* Note: N/A on UART4 & UART5 */
|
||||
#define USART_CR3_NACK (1 << 4)
|
||||
|
||||
/* HDSEL: Half-duplex selection */
|
||||
#define USART_CR3_HDSEL (1 << 3)
|
||||
|
||||
/* IRLP: IrDA low-power */
|
||||
#define USART_CR3_IRLP (1 << 2)
|
||||
|
||||
/* IREN: IrDA mode enable */
|
||||
#define USART_CR3_IREN (1 << 1)
|
||||
|
||||
/* EIE: Error interrupt enable */
|
||||
#define USART_CR3_EIE (1 << 0)
|
||||
|
||||
/* --- USART_BRR values ---------------------------------------------------- */
|
||||
|
||||
@ -344,90 +87,7 @@
|
||||
#define USART_GTPR_PSC_MASK 0xFF
|
||||
|
||||
|
||||
/* --- USART_RQR values --------------------------------------------------- */
|
||||
|
||||
/* TXFRQ: Transmit data flush request */
|
||||
#define USART_RQR_TXFRQ (1 << 4)
|
||||
|
||||
/* RXFRQ: Receive data flush request */
|
||||
#define USART_RQR_RXFRQ (1 << 3)
|
||||
|
||||
/* MMRQ: Mute mode request */
|
||||
#define USART_RQR_MMRQ (1 << 2)
|
||||
|
||||
/* SBKRQ: Send break request */
|
||||
#define USART_RQR_SBKRQ (1 << 1)
|
||||
|
||||
/* ABRRQ: Auto baud rate request */
|
||||
#define USART_RQR_ABKRQ (1 << 0)
|
||||
|
||||
/* --- USART_ISR values --------------------------------------------------- */
|
||||
|
||||
/* REACK: Receive enable acknowledge flag */
|
||||
#define USART_ISR_REACK (1 << 22)
|
||||
|
||||
/* TEACK: Transmit enable acknowledge flag */
|
||||
#define USART_ISR_TEACK (1 << 21)
|
||||
|
||||
/* WUF: Wakeup from Stop mode flag */
|
||||
#define USART_ISR_WUF (1 << 20)
|
||||
|
||||
/* RWU: Receiver wakeup from Mute mode */
|
||||
#define USART_ISR_RWU (1 << 19)
|
||||
|
||||
/* SBKF: Send break flag */
|
||||
#define USART_ISR_SBKF (1 << 18)
|
||||
|
||||
/* CMF: Character match flag */
|
||||
#define USART_ISR_CMF (1 << 17)
|
||||
|
||||
/* BUSY: Busy flag */
|
||||
#define USART_ISR_BUSY (1 << 16)
|
||||
|
||||
/* ABRF: Auto baud rate flag */
|
||||
#define USART_ISR_ABRF (1 << 15)
|
||||
|
||||
/* ABRE: Auto baud rate error */
|
||||
#define USART_ISR_ABRE (1 << 14)
|
||||
|
||||
/* EOBF: End of block flag */
|
||||
#define USART_ISR_EOBF (1 << 12)
|
||||
|
||||
/* RTOF: Receiver timeout */
|
||||
#define USART_ISR_RTOF (1 << 11)
|
||||
|
||||
/* CTS: CTS flag */
|
||||
#define USART_ISR_CTS (1 << 10)
|
||||
|
||||
/* CTSIF: CTS interrupt flag */
|
||||
#define USART_ISR_CTSIF (1 << 9)
|
||||
|
||||
/* LBDF: LIN break detection flag */
|
||||
#define USART_ISR_LBDF (1 << 8)
|
||||
|
||||
/* TXE: Transmit data register empty */
|
||||
#define USART_ISR_TXE (1 << 7)
|
||||
|
||||
/* TC: Transmission complete */
|
||||
#define USART_ISR_TC (1 << 6)
|
||||
|
||||
/* RXNE: Read data register not empty */
|
||||
#define USART_ISR_RXNE (1 << 5)
|
||||
|
||||
/* IDLE: Idle line detected */
|
||||
#define USART_ISR_IDLE (1 << 4)
|
||||
|
||||
/* ORE: Overrun error */
|
||||
#define USART_ISR_ORE (1 << 3)
|
||||
|
||||
/* NF: Noise detected flag */
|
||||
#define USART_ISR_NF (1 << 2)
|
||||
|
||||
/* FE: Framing error */
|
||||
#define USART_ISR_FE (1 << 1)
|
||||
|
||||
/* PE: Parity error */
|
||||
#define USART_ISR_PE (1 << 0)
|
||||
|
||||
/* --- USART_SR values ----------------------------------------------------- */
|
||||
/****************************************************************************/
|
||||
@ -468,43 +128,6 @@
|
||||
#define USART_SR_PE USART_ISR_PE
|
||||
/**@}*/
|
||||
|
||||
/* --- USART_ICR values --------------------------------------------------- */
|
||||
|
||||
/* WUCF: Wakeup from Stop mode clear flag */
|
||||
#define USART_ICR_WUCF (1 << 20)
|
||||
|
||||
/* CMCF: Character match clear flag */
|
||||
#define USART_ICR_CMCF (1 << 17)
|
||||
|
||||
/* EOBCF: End of timeout clear flag */
|
||||
#define USART_ICR_EOBCF (1 << 12)
|
||||
|
||||
/* RTOCF: Receiver timeout clear flag */
|
||||
#define USART_ICR_RTOCF (1 << 11)
|
||||
|
||||
/* CTSCF: CTS clear flag */
|
||||
#define USART_ICR_CTSCF (1 << 9)
|
||||
|
||||
/* LBDCF: LIN break detection clear flag */
|
||||
#define USART_ICR_LBDCF (1 << 8)
|
||||
|
||||
/* TCCF: Transmission complete clear flag */
|
||||
#define USART_ICR_TCCF (1 << 6)
|
||||
|
||||
/* IDLECF: Idle line detected clear flag */
|
||||
#define USART_ICR_IDLECF (1 << 4)
|
||||
|
||||
/* ORECF: Overrun error clear flag */
|
||||
#define USART_ICR_ORECF (1 << 3)
|
||||
|
||||
/* NCF: Noise detected clear flag */
|
||||
#define USART_ICR_NCF (1 << 2)
|
||||
|
||||
/* FECF: Framing error clear flag */
|
||||
#define USART_ICR_FECF (1 << 1)
|
||||
|
||||
/* PECF: Parity error clear flag */
|
||||
#define USART_ICR_PECF (1 << 0)
|
||||
|
||||
/* --- USART_RDR values --------------------------------------------------- */
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user