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Merge pull request #846 from UweBonnes/cortexm_halt

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Cortexm halt
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UweBonnes 2021-03-26 20:38:31 +01:00 committed by GitHub
commit fb8492a7e5
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3 changed files with 14 additions and 11 deletions
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15
src/target/adiv5.c
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@ -321,6 +321,9 @@ uint64_t adiv5_ap_read_pidr(ADIv5_AP_t *ap, uint32_t addr)
* - fails reading outside SYSROM when halted from WFI and * - fails reading outside SYSROM when halted from WFI and
* DBGMCU_CR not set. * DBGMCU_CR not set.
* *
* E.g. Stm32F0
* - fails reading DBGMCU when under reset
*
* Keep a copy of DEMCR at startup to restore with exit, to * Keep a copy of DEMCR at startup to restore with exit, to
* not interrupt tracing initiated by the CPU. * not interrupt tracing initiated by the CPU.
*/ */
@ -411,17 +414,8 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
if (addr == 0) /* No rom table on this AP */ if (addr == 0) /* No rom table on this AP */
return; return;
uint32_t cidr = adiv5_ap_read_id(ap, addr + CIDR0_OFFSET); uint32_t cidr = adiv5_ap_read_id(ap, addr + CIDR0_OFFSET);
if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) {
/* Maybe caused by a not halted CortexM */
if ((ap->idr & 0xf) == ARM_AP_TYPE_AHB) {
if (!cortexm_prepare(ap))
return; /* Halting failed! */
/* CPU now halted, read cidr again. */
cidr = adiv5_ap_read_id(ap, addr + CIDR0_OFFSET);
if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE)
return; return;
}
}
#if defined(ENABLE_DEBUG) #if defined(ENABLE_DEBUG)
char indent[recursion + 1]; char indent[recursion + 1];
@ -755,6 +749,9 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
extern void efm32_aap_probe(ADIv5_AP_t *); extern void efm32_aap_probe(ADIv5_AP_t *);
efm32_aap_probe(ap); efm32_aap_probe(ap);
/* Halt the device and release from reset if reset is active!*/
if (!ap->apsel && ((ap->idr & 0xf) == ARM_AP_TYPE_AHB))
cortexm_prepare(ap);
/* Should probe further here to make sure it's a valid target. /* Should probe further here to make sure it's a valid target.
* AP should be unref'd if not valid. * AP should be unref'd if not valid.
*/ */

2
src/target/cortexm.c
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@ -377,7 +377,7 @@ bool cortexm_probe(ADIv5_AP_t *ap)
target_check_error(t); target_check_error(t);
} }
#define PROBE(x) \ #define PROBE(x) \
do { if ((x)(t)) {target_halt_resume(t, 0); return true;} else target_check_error(t); } while (0) do { if ((x)(t)) {return true;} else target_check_error(t); } while (0)
switch (ap->ap_designer) { switch (ap->ap_designer) {
case AP_DESIGNER_FREESCALE: case AP_DESIGNER_FREESCALE:

6
src/target/stm32f1.c
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@ -155,6 +155,11 @@ bool gd32f1_probe(target *t)
bool stm32f1_probe(target *t) bool stm32f1_probe(target *t)
{ {
uint16_t stored_idcode = t->idcode;
if ((t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M0)
t->idcode = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
else
t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
size_t flash_size; size_t flash_size;
size_t block_size = 0x400; size_t block_size = 0x400;
switch(t->idcode) { switch(t->idcode) {
@ -227,6 +232,7 @@ bool stm32f1_probe(target *t)
block_size = 0x800; block_size = 0x800;
break; break;
default: /* NONE */ default: /* NONE */
t->idcode = stored_idcode;
return false; return false;
} }