[STM32F0:USART] Add support for USART peripheral
This commit is contained in:
BuFran
Piotr Esden-Tempski
parent
18c4d299c1
commit
fc02aa6162
304
include/libopencm3/stm32/f0/usart.h
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304
include/libopencm3/stm32/f0/usart.h
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/** @defgroup usart_defines USART Defines
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*
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* @brief <b>Defined Constants and Types for the STM32F0xx USART</b>
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*
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* @ingroup STM32F0xx_defines
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*
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* @version 1.0.0
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*
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* @date 2 July 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_USART_H
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#define LIBOPENCM3_USART_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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#define USART1 USART1_BASE
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#define USART2 USART2_BASE
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/* USART Registers ----------------------------------------------------------*/
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#define USART_CR1(usart_base) MMIO32(usart_base + 0x00)
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#define USART1_CR1 USART_CR1(USART1_BASE)
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#define USART2_CR1 USART_CR1(USART2_BASE)
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#define USART_CR2(usart_base) MMIO32(usart_base + 0x04)
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#define USART1_CR2 USART_CR2(USART1_BASE)
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#define USART2_CR2 USART_CR2(USART2_BASE)
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#define USART_CR3(usart_base) MMIO32(usart_base + 0x08)
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#define USART1_CR3 USART_CR3(USART1_BASE)
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#define USART2_CR3 USART_CR3(USART2_BASE)
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#define USART_BRR(usart_base) MMIO32(usart_base + 0x0c)
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#define USART1_BRR USART_BRR(USART1_BASE)
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#define USART2_BRR USART_BRR(USART2_BASE)
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#define USART_GTPR(usart_base) MMIO32(usart_base + 0x10)
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#define USART1_GTPR USART_GTPR(USART1_BASE)
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#define USART2_GTPR USART_GTPR(USART2_BASE)
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#define USART_RTOR(usart_base) MMIO32(usart_base + 0x14)
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#define USART1_RTOR USART_RTOR(USART1_BASE)
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#define USART2_RTOR USART_RTOR(USART2_BASE)
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#define USART_RQR(usart_base) MMIO32(usart_base + 0x18)
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#define USART1_RQR USART_RQR(USART1_BASE)
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#define USART2_RQR USART_RQR(USART2_BASE)
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#define USART_ISR(usart_base) MMIO32(usart_base + 0x1c)
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#define USART1_ISR USART_ISR(USART1_BASE)
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#define USART2_ISR USART_ISR(USART2_BASE)
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#define USART_ICR(usart_base) MMIO32(usart_base + 0x20)
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#define USART1_ICR USART_ICR(USART1_BASE)
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#define USART2_ICR USART_ICR(USART2_BASE)
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#define USART_RDR(usart_base) MMIO8(usart_base + 0x24)
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#define USART1_RDR USART_RDR(USART1_BASE)
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#define USART2_RDR USART_RDR(USART2_BASE)
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#define USART_TDR(usart_base) MMIO8(usart_base + 0x28)
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#define USART1_TDR USART_TDR(USART1_BASE)
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#define USART2_TDR USART_TDR(USART2_BASE)
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/* Register values ----------------------------------------------------------*/
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/* USART_CR1 Values ---------------------------------------------------------*/
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#define USART_CR1_EOBIE (1 << 27)
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#define USART_CR1_RTOIE (1 << 26)
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#define USART_CR1_DEAT_SHIFT 21
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#define USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT)
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#define USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT)
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#define USART_CR1_DEDT_SHIFT 16
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#define USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT)
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#define USART_CR1_DEDT_VAL(x) ((x) << USART_CR1_DEDT_SHIFT)
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#define USART_CR1_OVER8 (1 << 15)
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#define USART_CR1_CMIE (1 << 14)
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#define USART_CR1_MME (1 << 13)
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#define USART_CR1_M (1 << 12)
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#define USART_CR1_WAKE (1 << 11)
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#define USART_CR1_PCE (1 << 10)
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#define USART_CR1_PS (1 << 9)
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#define USART_CR1_PEIE (1 << 8)
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#define USART_CR1_TXEIE (1 << 7)
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#define USART_CR1_TCIE (1 << 6)
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#define USART_CR1_RXNEIE (1 << 5)
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#define USART_CR1_IDLEIE (1 << 4)
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#define USART_CR1_TE (1 << 3)
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#define USART_CR1_RE (1 << 2)
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#define USART_CR1_UESM (1 << 1)
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#define USART_CR1_UE (1 << 0)
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/* USART_CR2 Values ---------------------------------------------------------*/
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#define USART_CR2_ADD_SHIFT 24
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#define USART_CR2_ADD (0xFF << USART_CR2_ADD_SHIFT)
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#define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)
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#define USART_CR2_RTOEN (1 << 23)
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#define USART_CR2_ABRMOD_SHIFT 21
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#define USART_CR2_ABRMOD (3 << USART_CR2_ABRMOD_SHIFT)
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#define USART_CR2_ABRMOD_STARTBIT (0 << USART_CR2_ABRMOD_SHIFT)
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#define USART_CR2_ABRMOD_FALLTOFALL (1 << USART_CR2_ABRMOD_SHIFT)
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#define USART_CR2_ABREN (1 << 20)
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#define USART_CR2_MSBFIRST (1 << 19)
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#define USART_CR2_DATAINV (1 << 18)
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#define USART_CR2_TXINV (1 << 17)
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#define USART_CR2_RXINV (1 << 16)
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#define USART_CR2_SWAP (1 << 15)
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#define USART_CR2_LINEN (1 << 14)
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#define USART_CR2_STOP_SHIFT 12
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#define USART_CR2_STOP (3 << USART_CR2_STOP_SHIFT)
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#define USART_CR2_STOP_1_0BIT (0 << USART_CR2_STOP_SHIFT)
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#define USART_CR2_STOP_2_0BIT (2 << USART_CR2_STOP_SHIFT)
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#define USART_CR2_STOP_1_5BIT (3 << USART_CR2_STOP_SHIFT)
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#define USART_CR2_CLKEN (1 << 11)
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#define USART_CR2_CPOL (1 << 10)
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#define USART_CR2_CPHA (1 << 9)
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#define USART_CR2_LBCL (1 << 8)
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#define USART_CR2_LBIDE (1 << 6)
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#define USART_CR2_LBDL (1 << 5)
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#define USART_CR2_ADDM (1 << 4)
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/* USART_CR3 Values ---------------------------------------------------------*/
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#define USART_CR3_WUFIE (1 << 22)
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#define USART_CR3_WUS_SHIFT 20
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#define USART_CR3_WUS (3 << USART_CR3_WUS_SHIFT)
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#define USART_CR3_WUS_ADDRMATCH (0 << USART_CR3_WUS_SHIFT)
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#define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT)
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#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT)
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#define USART_CR3_SCARCNT_SHIFT 17
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#define USART_CR3_SCARCNT (7 << USART_CR3_SCARCNT_SHIFT)
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#define USART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT)
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#define USART_CR3_SCARCNT_VAL(x) ((x) << USART_CR3_SCARCNT_SHIFT)
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#define USART_CR3_DEP (1 << 15)
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#define USART_CR3_DEM (1 << 14)
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#define USART_CR3_DDRE (1 << 13)
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#define USART_CR3_OVRDIS (1 << 12)
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#define USART_CR3_ONEBIT (1 << 11)
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#define USART_CR3_CTSIE (1 << 10)
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#define USART_CR3_CTSE (1 << 9)
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#define USART_CR3_RTSE (1 << 8)
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#define USART_CR3_DMAT (1 << 7)
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#define USART_CR3_DMAR (1 << 6)
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#define USART_CR3_SCEN (1 << 5)
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#define USART_CR3_NACK (1 << 4)
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#define USART_CR3_HDSEL (1 << 3)
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#define USART_CR3_IRLP (1 << 2)
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#define USART_CR3_IREN (1 << 1)
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#define USART_CR3_EIE (1 << 0)
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/* USART_GTPR Values --------------------------------------------------------*/
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#define USART_GTPR_GT_SHIFT 8
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#define USART_GTPR_GT (0xFF << USART_GTPR_GT_SHIFT)
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#define USART_GTPR_GT_VAL(x) ((x) << USART_GTPR_GT_SHIFT)
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#define USART_GTPR_PSC_SHIFT 0
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#define USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT)
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#define USART_GTPR_PSC_VAL(x) ((x) << USART_GTPR_PSC_SHIFT)
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/* USART_RTOR Values --------------------------------------------------------*/
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#define USART_RTOR_BLEN_SHIFT 24
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#define USART_RTOR_BLEN (0xFF << USART_RTOR_BLEN_SHIFT)
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#define USART_RTOR_BLEN_VAL(x) ((x) << USART_RTOR_BLEN_SHIFT)
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#define USART_RTOR_RTO_SHIFT 0
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#define USART_RTOR_RTO (0xFF << USART_RTOR_RTO_SHIFT)
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#define USART_RTOR_RTO_VAL(x) ((x) << USART_RTOR_RTO_SHIFT)
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/* USART_RQR Values ---------------------------------------------------------*/
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#define USART_RQR_TXFRQ (1 << 4)
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#define USART_RQR_RXFRQ (1 << 3)
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#define USART_RQR_MMRQ (1 << 2)
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#define USART_RQR_SBKRQ (1 << 1)
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#define USART_RQR_ABRRQ (1 << 0)
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/* USART_ISR Values ---------------------------------------------------------*/
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#define USART_ISR_REACK (1 << 22)
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#define USART_ISR_TEACK (1 << 21)
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#define USART_ISR_WUF (1 << 20)
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#define USART_ISR_RWU (1 << 19)
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#define USART_ISR_SBKF (1 << 18)
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#define USART_ISR_CMF (1 << 17)
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#define USART_ISR_BUSY (1 << 16)
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#define USART_ISR_ABRF (1 << 15)
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#define USART_ISR_ABRE (1 << 14)
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#define USART_ISR_EOBF (1 << 12)
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#define USART_ISR_RTOF (1 << 11)
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#define USART_ISR_CTS (1 << 10)
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#define USART_ISR_CTSIF (1 << 9)
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#define USART_ISR_LBDF (1 << 8)
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#define USART_ISR_TXE (1 << 7)
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#define USART_ISR_TC (1 << 6)
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#define USART_ISR_RXNE (1 << 5)
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#define USART_ISR_IDLE (1 << 4)
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#define USART_ISR_ORE (1 << 3)
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#define USART_ISR_NF (1 << 2)
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#define USART_ISR_FE (1 << 1)
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#define USART_ISR_PE (1 << 0)
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/* USART_ICR Values ---------------------------------------------------------*/
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#define USART_ICR_WUCF (1 << 20)
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#define USART_ICR_CMCF (1 << 17)
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#define USART_ICR_EOBCF (1 << 12)
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#define USART_ICR_RTOCF (1 << 11)
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#define USART_ICR_CTSCF (1 << 9)
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#define USART_ICR_LBDCF (1 << 8)
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#define USART_ICR_TCCF (1 << 6)
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#define USART_ICR_IDLECF (1 << 4)
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#define USART_ICR_ORECF (1 << 3)
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#define USART_ICR_NCF (1 << 2)
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#define USART_ICR_FECF (1 << 1)
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#define USART_ICR_PECF (1 << 0)
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#define USART_PARITY (USART_CR1_PCE | USART_CR1_PS)
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#define USART_PARITY_NONE (0)
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#define USART_PARITY_EVEN (USART_CR1_PCE)
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#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
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#define USART_MODE (USART_CR1_TE | USART_CR1_RE)
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#define USART_MODE_NONE (0)
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#define USART_MODE_RX (USART_CR1_RE)
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#define USART_MODE_TX (USART_CR1_TE)
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#define USART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE)
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#define USART_FLOWCONTROL (USART_CR3_RTSE | USART_CR3_CTSE)
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#define USART_FLOWCONTROL_NONE (0)
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#define USART_FLOWCONTROL_RTS (USART_CR3_RTSE)
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#define USART_FLOWCONTROL_CTS (USART_CR3_CTSE)
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#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
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BEGIN_DECLS
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void usart_set_baudrate(uint32_t usart, uint32_t baud);
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void usart_set_databits(uint32_t usart, uint32_t bits);
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void usart_set_stopbits(uint32_t usart, uint32_t stopbits);
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void usart_set_parity(uint32_t usart, uint32_t parity);
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void usart_set_mode(uint32_t usart, uint32_t mode);
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void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol);
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void usart_enable(uint32_t usart);
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void usart_disable(uint32_t usart);
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void usart_send(uint32_t usart, uint8_t data);
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uint8_t usart_recv(uint32_t usart);
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void usart_wait_send_ready(uint32_t usart);
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void usart_wait_recv_ready(uint32_t usart);
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void usart_send_blocking(uint32_t usart, uint8_t data);
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uint8_t usart_recv_blocking(uint32_t usart);
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void usart_enable_rx_dma(uint32_t usart);
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void usart_disable_rx_dma(uint32_t usart);
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void usart_enable_tx_dma(uint32_t usart);
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void usart_disable_tx_dma(uint32_t usart);
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void usart_enable_rx_interrupt(uint32_t usart);
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void usart_disable_rx_interrupt(uint32_t usart);
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void usart_enable_tx_interrupt(uint32_t usart);
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void usart_disable_tx_interrupt(uint32_t usart);
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void usart_enable_error_interrupt(uint32_t usart);
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void usart_disable_error_interrupt(uint32_t usart);
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bool usart_get_flag(uint32_t usart, uint32_t flag);
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bool usart_get_interrupt_source(uint32_t usart, uint32_t flag);
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END_DECLS
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#endif
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@ -17,7 +17,9 @@
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#if defined(STM32F1)
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#if defined(STM32F0)
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# include <libopencm3/stm32/f0/usart.h>
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#elif defined(STM32F1)
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# include <libopencm3/stm32/f1/usart.h>
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#elif defined(STM32F2)
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# include <libopencm3/stm32/f2/usart.h>
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@ -33,7 +33,7 @@ CFLAGS = -Os -g \
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ARFLAGS = rcs
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OBJS = flash.o rcc.o
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OBJS = flash.o rcc.o usart.o
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OBJS += gpio_common_all.o gpio_common_f234.o crc_common_all.o \
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pwr_common_all.o
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429
lib/stm32/f0/usart.c
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429
lib/stm32/f0/usart.c
Normal file
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/** @defgroup usart_file USART
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*
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* @ingroup STM32F0xx
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*
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* @brief <b>libopencm3 STM32F0xx USART</b>
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*
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* @version 1.0.0
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*
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* @date 7 Jul 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/usart.h>
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#include <libopencm3/stm32/rcc.h>
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/*---------------------------------------------------------------------------*/
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/** @brief USART Set Baudrate.
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*
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* @param[in] usart unsigned 32 bit. USART block register address base @ref
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* usart_reg_base
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* @param[in] baud unsigned 32 bit. Baud rate specified in Hz.
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*/
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void usart_set_baudrate(uint32_t usart, uint32_t baud)
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{
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uint32_t clock = rcc_ppre_frequency;
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||||
if (usart == USART1) {
|
||||
clock = rcc_ppre_frequency;
|
||||
/* TODO selective PCLK, SYSCLK, HSI or LSE */
|
||||
}
|
||||
|
||||
/* TODO check oversampling 16 */
|
||||
USART_BRR(usart) = ((2 * clock) + baud) / (2 * baud);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Set Word Length.
|
||||
*
|
||||
* The word length is set to 8 or 9 bits. Note that the last bit will be a
|
||||
* parity bit if parity is enabled, in which case the data length will be 7
|
||||
* or 8 bits respectively.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
* @param[in] bits unsigned 32 bit. Word length in bits 8 or 9.
|
||||
*/
|
||||
|
||||
void usart_set_databits(uint32_t usart, uint32_t bits)
|
||||
{
|
||||
if (bits == 8) {
|
||||
USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */
|
||||
} else {
|
||||
USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Set Stop Bit(s).
|
||||
*
|
||||
* The stop bits are specified as 0.5, 1, 1.5 or 2.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
* @param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits.
|
||||
*/
|
||||
|
||||
void usart_set_stopbits(uint32_t usart, uint32_t stopbits)
|
||||
{
|
||||
USART_CR2(usart) = (USART_CR2(usart) & ~USART_CR2_STOP) | stopbits;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Set Parity.
|
||||
*
|
||||
* The parity bit can be selected as none, even or odd.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
* @param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity.
|
||||
*/
|
||||
|
||||
void usart_set_parity(uint32_t usart, uint32_t parity)
|
||||
{
|
||||
USART_CR1(usart) = (USART_CR1(usart) & ~USART_PARITY) | parity;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Set Rx/Tx Mode.
|
||||
*
|
||||
* The mode can be selected as Rx only, Tx only or Rx+Tx.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
* @param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode.
|
||||
*/
|
||||
|
||||
void usart_set_mode(uint32_t usart, uint32_t mode)
|
||||
{
|
||||
USART_CR1(usart) = (USART_CR1(usart) & ~USART_MODE) | mode;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Set Hardware Flow Control.
|
||||
*
|
||||
* The flow control bit can be selected as none, RTS, CTS or RTS+CTS.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
* @param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref
|
||||
* usart_cr3_flowcontrol.
|
||||
*/
|
||||
|
||||
void usart_set_flow_control(uint32_t usart, uint32_t flowctrl)
|
||||
{
|
||||
USART_CR3(usart) = (USART_CR3(usart) & ~USART_FLOWCONTROL) | flowctrl;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Enable.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_enable(uint32_t usart)
|
||||
{
|
||||
USART_CR1(usart) |= USART_CR1_UE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Disable.
|
||||
*
|
||||
* At the end of the current frame, the USART is disabled to reduce power.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_disable(uint32_t usart)
|
||||
{
|
||||
USART_CR1(usart) &= ~USART_CR1_UE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Send a Data Word.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
* @param[in] data unsigned 16 bit.
|
||||
*/
|
||||
|
||||
void usart_send(uint32_t usart, uint8_t data)
|
||||
{
|
||||
USART_TDR(usart) = data;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Read a Received Data Word.
|
||||
*
|
||||
* If parity is enabled the MSB (bit 7 or 8 depending on the word length) is
|
||||
* the parity bit.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
* @returns unsigned 16 bit data word.
|
||||
*/
|
||||
|
||||
uint8_t usart_recv(uint32_t usart)
|
||||
{
|
||||
/* Receive data. */
|
||||
return USART_RDR(usart);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Wait for Transmit Data Buffer Empty
|
||||
*
|
||||
* Blocks until the transmit data buffer becomes empty and is ready to accept
|
||||
* the next data word.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_wait_send_ready(uint32_t usart)
|
||||
{
|
||||
/* Wait until the data has been transferred into the shift register. */
|
||||
while ((USART_ISR(usart) & USART_ISR_TXE) == 0);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Wait for Received Data Available
|
||||
*
|
||||
* Blocks until the receive data buffer holds a valid received data word.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_wait_recv_ready(uint32_t usart)
|
||||
{
|
||||
/* Wait until the data is ready to be received. */
|
||||
while ((USART_ISR(usart) & USART_ISR_RXNE) == 0);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Send Data Word with Blocking
|
||||
*
|
||||
* Blocks until the transmit data buffer becomes empty then writes the next
|
||||
* data word for transmission.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
* @param[in] data unsigned 16 bit.
|
||||
*/
|
||||
|
||||
void usart_send_blocking(uint32_t usart, uint8_t data)
|
||||
{
|
||||
usart_wait_send_ready(usart);
|
||||
usart_send(usart, data);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Read a Received Data Word with Blocking.
|
||||
*
|
||||
* Wait until a data word has been received then return the word.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
* @returns unsigned 16 bit data word.
|
||||
*/
|
||||
|
||||
uint8_t usart_recv_blocking(uint32_t usart)
|
||||
{
|
||||
usart_wait_recv_ready(usart);
|
||||
|
||||
return usart_recv(usart);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Receiver DMA Enable.
|
||||
*
|
||||
* DMA is available on:
|
||||
* @li USART1 Rx DMA1 channel 3 or 5.
|
||||
* @li USART2 Rx DMA1 channel 5.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_enable_rx_dma(uint32_t usart)
|
||||
{
|
||||
USART_CR3(usart) |= USART_CR3_DMAR;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Receiver DMA Disable.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_disable_rx_dma(uint32_t usart)
|
||||
{
|
||||
USART_CR3(usart) &= ~USART_CR3_DMAR;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Transmitter DMA Enable.
|
||||
*
|
||||
* DMA is available on:
|
||||
* @li USART1 Tx DMA1 channel 2 or 4.
|
||||
* @li USART2 Tx DMA1 channel 4.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_enable_tx_dma(uint32_t usart)
|
||||
{
|
||||
USART_CR3(usart) |= USART_CR3_DMAT;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Transmitter DMA Disable.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_disable_tx_dma(uint32_t usart)
|
||||
{
|
||||
USART_CR3(usart) &= ~USART_CR3_DMAT;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Receiver Interrupt Enable.
|
||||
|
||||
@param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_enable_rx_interrupt(uint32_t usart)
|
||||
{
|
||||
USART_CR1(usart) |= USART_CR1_RXNEIE;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Receiver Interrupt Disable.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_disable_rx_interrupt(uint32_t usart)
|
||||
{
|
||||
USART_CR1(usart) &= ~USART_CR1_RXNEIE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Transmitter Interrupt Enable.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_enable_tx_interrupt(uint32_t usart)
|
||||
{
|
||||
USART_CR1(usart) |= USART_CR1_TXEIE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Transmitter Interrupt Disable.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_disable_tx_interrupt(uint32_t usart)
|
||||
{
|
||||
USART_CR1(usart) &= ~USART_CR1_TXEIE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Error Interrupt Enable.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_enable_error_interrupt(uint32_t usart)
|
||||
{
|
||||
USART_CR3(usart) |= USART_CR3_EIE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Error Interrupt Disable.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
*/
|
||||
|
||||
void usart_disable_error_interrupt(uint32_t usart)
|
||||
{
|
||||
USART_CR3(usart) &= ~USART_CR3_EIE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Read a Status Flag.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
* @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags.
|
||||
* @returns boolean: flag set.
|
||||
*/
|
||||
|
||||
bool usart_get_flag(uint32_t usart, uint32_t flag)
|
||||
{
|
||||
return ((USART_ISR(usart) & flag) != 0);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief USART Return Interrupt Source.
|
||||
*
|
||||
* Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was
|
||||
* set and the interrupt was enabled. If the specified flag is not an interrupt
|
||||
* flag, the function returns false.
|
||||
*
|
||||
* @param[in] usart unsigned 32 bit. USART block register address base @ref
|
||||
* usart_reg_base
|
||||
* @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags.
|
||||
* @returns boolean: flag and interrupt enable both set.
|
||||
*/
|
||||
|
||||
bool usart_get_interrupt_source(uint32_t usart, uint32_t flag)
|
||||
{
|
||||
uint32_t flag_set = (USART_ISR(usart) & flag);
|
||||
/* IDLE, RXNE, TC, TXE interrupts */
|
||||
if ((flag >= USART_ISR_IDLE) && (flag <= USART_ISR_TXE)) {
|
||||
return ((flag_set & USART_CR1(usart)) != 0);
|
||||
/* Overrun error */
|
||||
} else if (flag == USART_ISR_ORE) {
|
||||
return flag_set && (USART_CR3(usart) & USART_CR3_CTSIE);
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user