From fcd945a529009496b142dbde560cd930f5bd9b42 Mon Sep 17 00:00:00 2001
From: Fredrik Ahlberg <fredrik@z80.se>
Date: Sun, 12 Jul 2020 12:08:22 +0200
Subject: [PATCH] cortexm: Read CPUID to identify core version

---
 src/target/cortexm.c | 36 +++++++++++++++++++++++++++---------
 src/target/cortexm.h |  1 +
 2 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/src/target/cortexm.c b/src/target/cortexm.c
index 00668d51..c3bc0dfb 100644
--- a/src/target/cortexm.c
+++ b/src/target/cortexm.c
@@ -294,7 +294,6 @@ bool cortexm_probe(ADIv5_AP_t *ap, bool forced)
 	}
 
 	adiv5_ap_ref(ap);
-	uint32_t identity = ap->idr & 0xff;
 	struct cortexm_priv *priv = calloc(1, sizeof(*priv));
 	if (!priv) {			/* calloc failed: heap exhaustion */
 		DEBUG_WARN("calloc: failed in %s\n", __func__);
@@ -310,18 +309,37 @@ bool cortexm_probe(ADIv5_AP_t *ap, bool forced)
 	t->mem_write = cortexm_mem_write;
 
 	t->driver = cortexm_driver_str;
-	switch (identity) {
-	case 0x11: /* M3/M4 */
-		t->core = "M3/M4";
+
+	uint32_t cpuid = target_mem_read32(t, CORTEXM_CPUID);
+	uint16_t partno = (cpuid >> 4) & 0xfff;
+
+	switch (partno) {
+	case 0xd21:
+		t->core = "M33";
 		break;
-	case 0x21: /* M0 */
-		t->core = "M0";
+
+	case 0xd20:
+		t->core = "M23";
 		break;
-	case 0x31: /* M0+ */
+
+	case 0xc23:
+		t->core = "M3";
+		break;
+
+	case 0xc24:
+		t->core = "M4";
+		break;
+
+	case 0xc27:
+		t->core = "M7";
+		break;
+
+	case 0xc60:
 		t->core = "M0+";
 		break;
-	case 0x01: /* M7 */
-		t->core = "M7";
+
+	case 0xc20:
+		t->core = "M0";
 		break;
 	}
 
diff --git a/src/target/cortexm.h b/src/target/cortexm.h
index 01077620..95952f5b 100644
--- a/src/target/cortexm.h
+++ b/src/target/cortexm.h
@@ -28,6 +28,7 @@ extern long cortexm_wait_timeout;
 
 #define CORTEXM_SCS_BASE	(CORTEXM_PPB_BASE + 0xE000)
 
+#define CORTEXM_CPUID		(CORTEXM_SCS_BASE + 0xD00)
 #define CORTEXM_AIRCR		(CORTEXM_SCS_BASE + 0xD0C)
 #define CORTEXM_CFSR		(CORTEXM_SCS_BASE + 0xD28)
 #define CORTEXM_HFSR		(CORTEXM_SCS_BASE + 0xD2C)