diff --git a/src/platforms/stlink/platform.c b/src/platforms/stlink/platform.c
index a8797912..cb549002 100644
--- a/src/platforms/stlink/platform.c
+++ b/src/platforms/stlink/platform.c
@@ -68,9 +68,8 @@ void platform_init(void)
 	              GPIO_CNF_OUTPUT_PUSHPULL, TCK_PIN);
 	gpio_set_mode(TDI_PORT, GPIO_MODE_OUTPUT_50_MHZ,
 	              GPIO_CNF_OUTPUT_PUSHPULL, TDI_PIN);
-	gpio_set(SRST_PORT, srst_pin);
-	gpio_set_mode(SRST_PORT, GPIO_MODE_OUTPUT_50_MHZ,
-	              GPIO_CNF_OUTPUT_OPENDRAIN, srst_pin);
+
+	platform_srst_set_val(false);
 
 	gpio_set_mode(LED_PORT, GPIO_MODE_OUTPUT_2_MHZ,
 	              GPIO_CNF_OUTPUT_PUSHPULL, led_idle_run);
@@ -90,21 +89,17 @@ void platform_init(void)
 
 void platform_srst_set_val(bool assert)
 {
-	uint32_t crl = GPIOB_CRL;
-	uint32_t shift = (srst_pin == GPIO0) ? 0 : 4;
-	uint32_t mask = 0xf << shift;
-	crl &= ~mask;
 	if (assert) {
-		/* Set SRST as Open-Drain, 50 Mhz, low.*/
-		GPIOB_BRR = srst_pin;
-		GPIOB_CRL = crl | (7 << shift);
+		gpio_set_mode(SRST_PORT, GPIO_MODE_OUTPUT_50_MHZ,
+		              GPIO_CNF_OUTPUT_OPENDRAIN, srst_pin);
+		gpio_clear(SRST_PORT, srst_pin);
+		while (gpio_get(SRST_PORT, srst_pin)) {};
 	} else {
-		/* Set SRST as input, pull-up.
-		 * SRST might be unconnected, e.g on Nucleo-P!*/
-		GPIOB_CRL = crl | (8 << shift);
-		GPIOB_BSRR = srst_pin;
+		gpio_set_mode(SRST_PORT, GPIO_MODE_INPUT,
+			GPIO_CNF_INPUT_PULL_UPDOWN, srst_pin);
+		gpio_set(SRST_PORT, srst_pin);
+		while (!gpio_get(SRST_PORT, srst_pin)) {};
 	}
-	while (gpio_get(SRST_PORT, srst_pin) == assert) {};
 }
 
 bool platform_srst_get_val()
diff --git a/src/target/adiv5_swdp.c b/src/target/adiv5_swdp.c
index 8fac22f4..c61e4c3e 100644
--- a/src/target/adiv5_swdp.c
+++ b/src/target/adiv5_swdp.c
@@ -170,6 +170,17 @@ static uint32_t adiv5_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW,
 			raise_exception(EXCEPTION_ERROR, "SWDP Parity error");
 	} else {
 		swdptap_seq_out_parity(value, 32);
+		/* RM0377 Rev. 8 Chapter 27.5.4 for STM32L0x1 states:
+		 * Because of the asynchronous clock domains SWCLK and HCLK,
+		 * two extra SWCLK cycles are needed after a write transaction
+		 * (after the parity bit) to make the write effective
+		 * internally. These cycles should be applied while driving
+		 * the line low (IDLE state)
+		 * This is particularly important when writing the CTRL/STAT
+		 * for a power-up request. If the next transaction (requiring
+		 * a power-up) occurs immediately, it will fail.
+		 */
+		swdptap_seq_out(0, 2);
 	}
 
 	return response;
diff --git a/src/target/cortexm.c b/src/target/cortexm.c
index 8de881cd..3010daa5 100644
--- a/src/target/cortexm.c
+++ b/src/target/cortexm.c
@@ -414,8 +414,6 @@ void cortexm_detach(target *t)
 
 	/* Disable debug */
 	target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY);
-	/* Add some clock cycles to get the CPU running again.*/
-	target_mem_read32(t, 0);
 }
 
 enum { DB_DHCSR, DB_DCRSR, DB_DCRDR, DB_DEMCR };
diff --git a/src/target/nrf51.c b/src/target/nrf51.c
index cefbcc3e..95c5f0d5 100644
--- a/src/target/nrf51.c
+++ b/src/target/nrf51.c
@@ -166,7 +166,8 @@ bool nrf51_probe(target *t)
 	case 0x00AC: /* nRF52832 Preview QFAA BA0 */
 	case 0x00C7: /* nRF52832 (rev 1) QFAA B00 */
 	case 0x00E3: /* nRF52832 (rev 1) CIAA B?? */
-	case 0x0139: /* nRF82832 (rev 2) ??AA B?0 */
+	case 0x0139: /* nRF52832 (rev 2) ??AA B?0 */
+	case 0x014F: /* nRF52832 (rev 2) CIAA E1  */
 		t->driver = "Nordic nRF52";
 		target_add_ram(t, 0x20000000, 64*1024);
 		nrf51_add_flash(t, 0x00000000, 512*1024, NRF52_PAGE_SIZE);