diff --git a/lib/stm32/f0/rcc.c b/lib/stm32/f0/rcc.c
index 5d14df42..09f3bdcd 100644
--- a/lib/stm32/f0/rcc.c
+++ b/lib/stm32/f0/rcc.c
@@ -493,7 +493,7 @@ void rcc_clock_setup_in_hsi_out_16mhz(void)
 	/* 8MHz * 4 / 2 = 16MHz	 */
 	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL4);
 
-	RCC_CFGR &= RCC_CFGR_PLLSRC;
+	RCC_CFGR &= ~RCC_CFGR_PLLSRC;
 
 	rcc_osc_on(PLL);
 	rcc_wait_for_osc_ready(PLL);
@@ -518,7 +518,7 @@ void rcc_clock_setup_in_hsi_out_24mhz(void)
 	/* 8MHz * 6 / 2 = 24MHz	 */
 	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL6);
 
-	RCC_CFGR &= RCC_CFGR_PLLSRC;
+	RCC_CFGR &= ~RCC_CFGR_PLLSRC;
 
 	rcc_osc_on(PLL);
 	rcc_wait_for_osc_ready(PLL);
@@ -539,10 +539,10 @@ void rcc_clock_setup_in_hsi_out_32mhz(void)
 
 	flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
 
-	/* 8MHz * 8 / 2 = 32MHz	 */
+	/* 8MHz * 8 / 2 = 32MHz	*/
 	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL8);
 
-	RCC_CFGR &= RCC_CFGR_PLLSRC;
+	RCC_CFGR &= ~RCC_CFGR_PLLSRC;
 
 	rcc_osc_on(PLL);
 	rcc_wait_for_osc_ready(PLL);
@@ -563,10 +563,10 @@ void rcc_clock_setup_in_hsi_out_40mhz(void)
 
 	flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
 
-	/* 8MHz * 10 / 2 = 40MHz	 */
+	/* 8MHz * 10 / 2 = 40MHz */
 	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL10);
 
-	RCC_CFGR &= RCC_CFGR_PLLSRC;
+	RCC_CFGR &= ~RCC_CFGR_PLLSRC;
 
 	rcc_osc_on(PLL);
 	rcc_wait_for_osc_ready(PLL);
@@ -587,10 +587,10 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
 
 	flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
 
-	/* 8MHz * 12 / 2 = 48MHz	 */
+	/* 8MHz * 12 / 2 = 48MHz */
 	rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_MUL12);
 
-	RCC_CFGR &= RCC_CFGR_PLLSRC;
+	RCC_CFGR &= ~RCC_CFGR_PLLSRC;
 
 	rcc_osc_on(PLL);
 	rcc_wait_for_osc_ready(PLL);