stm32:l4: rcc: Add helper functions
Add functions for PLL output and 48MHz clock source selection
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@ -962,6 +962,8 @@ void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pl
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uint32_t rcc_system_clock_source(void);
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void rcc_set_msi_range(uint32_t msi_range);
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void rcc_set_msi_range_standby(uint32_t msi_range);
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void rcc_pll_output_enable(uint32_t pllout);
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void rcc_set_clock48_source(uint32_t clksel);
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END_DECLS
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@ -369,4 +369,33 @@ void rcc_set_msi_range_standby(uint32_t msi_range)
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RCC_CSR = reg;
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}
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/** Enable PLL Output
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*
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* - P (RCC_PLLCFGR_PLLPEN)
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* - Q (RCC_PLLCFGR_PLLQEN)
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* - R (RCC_PLLCFGR_PLLREN)
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*
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* @param pllout One or more of the definitions above
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*/
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void rcc_pll_output_enable(uint32_t pllout)
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{
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RCC_PLLCFGR |= pllout;
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}
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/** Set clock source for 48MHz clock
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*
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* The 48 MHz clock is derived from one of the four following sources:
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* - main PLL VCO (RCC_CCIPR_CLK48SEL_PLL)
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* - PLLSAI1 VCO (RCC_CCIPR_CLK48SEL_PLLSAI1Q)
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* - MSI clock (RCC_CCIPR_CLK48SEL_MSI)
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* - HSI48 internal oscillator (RCC_CCIPR_CLK48SEL_HSI48)
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*
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* @param clksel One of the definitions above
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*/
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void rcc_set_clock48_source(uint32_t clksel)
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{
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RCC_CCIPR &= ~(RCC_CCIPR_CLK48SEL_MASK << RCC_CCIPR_CLK48SEL_SHIFT);
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RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT);
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}
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/**@}*/
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