lpc17xx: clock: Add basic clock control definitions
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Silvio Gissi
Karl Palsson
parent
91dca33789
commit
ff8e2743e8
160
include/libopencm3/lpc17xx/clock.h
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160
include/libopencm3/lpc17xx/clock.h
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/** @defgroup clock_defines Clock Defines
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@brief <b>Defined Constants and Types for the LPC17xx Clock</b>
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@ingroup LPC17xx_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2013 Silvio Gissi <silvio.gissi@outlook.com>
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@date 17 August 2013
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Silvio Gissi <silvio.gissi@outlook.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC17XX_CLOCK_H
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#define LPC17XX_CLOCK_H
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#include <libopencm3/lpc17xx/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- Clock registers ----------------------------------------------------- */
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/* System Control and Status */
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#define CLK_SCS MMIO32(SYSCON_BASE + 0x1a0)
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/* Clock Source Selection */
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#define CLK_CLKSRCSEL MMIO32(SYSCON_BASE + 0x10c)
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/* PLL0: Main */
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#define CLK_PLL0CON MMIO32(SYSCON_BASE + 0x080)
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#define CLK_PLL0CFG MMIO32(SYSCON_BASE + 0x084)
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#define CLK_PLL0STAT MMIO32(SYSCON_BASE + 0x088)
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#define CLK_PLL0FEED MMIO32(SYSCON_BASE + 0x08c)
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/* PLL1: USB */
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#define CLK_PLL1CON MMIO32(SYSCON_BASE + 0x0a0)
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#define CLK_PLL1CFG MMIO32(SYSCON_BASE + 0x0a4)
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#define CLK_PLL1STAT MMIO32(SYSCON_BASE + 0x0a8)
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#define CLK_PLL1FEED MMIO32(SYSCON_BASE + 0x0ac)
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/* Clock Dividers */
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#define CLK_CCLKCFG MMIO32(SYSCON_BASE + 0x104)
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#define CLK_USBCLKCFG MMIO32(SYSCON_BASE + 0x108)
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#define CLK_PCLKSEL0 MMIO32(SYSCON_BASE + 0x1a8)
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#define CLK_PCLKSEL1 MMIO32(SYSCON_BASE + 0x1ac)
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/* Clock Output */
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#define CLK_CLKOUTCFG MMIO32(SYSCON_BASE + 0x1c8)
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/* CLK_SCS Values*/
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/* Reserved: [3:0] */
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#define CLK_SCS_OSCRANGE_01_TO_20MHZ (0)
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#define CLK_SCS_OSCRANGE_15_TO_25MHZ (1 << 4)
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#define CLK_SCS_OSCEN (1 << 5)
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#define CLK_SCS_OSCSTAT (1 << 6)
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/* Reserved: [31:7] */
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/* CLK_CLKSRCSEL Values*/
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#define CLK_CLKSRCSEL_IRC (0)
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#define CLK_CLKSRCSEL_MAIN (1 << 0)
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#define CLK_CLKSRCSEL_RTC (1 << 1)
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/* Reserved: value 11b */
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/* Reserved: [31:2] */
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/* CLK_PLL0CON and CLK_PLL1CON Values */
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#define CLK_PLLCON_ENABLE (1 << 0)
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#define CLK_PLLCON_CONNECT (1 << 1)
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/* Reserved: [31:2] */
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/* CLK_PLL0CFG and CLK_PLL0STAT Values */
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#define CLK_PLL0_MSEL_SHIFT 0
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#define CLK_PLL0_MSEL_MASK 0x7fff
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/* Reserved: [15] */
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#define CLK_PLL0_NSEL_SHIFT 16
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#define CLK_PLL0_NSEL_MASK 0xff
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/* CFG Reserved: [31:24] */
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#define CLK_PLL0STAT_ENABLE (1 << 24)
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#define CLK_PLL0STAT_CONNECT (1 << 25)
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#define CLK_PLL0STAT_PLOCK (1 << 26)
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/* STAT Reserved: [31:27] */
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/* CLK_PLL1CFG and CLK_PLL1STAT Values */
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#define CLK_PLL1_MSEL_SHIFT 0
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#define CLK_PLL1_MSEL_MASK 0x1f
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#define CLK_PLL1_PSEL_SHIFT 5
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#define CLK_PLL1_PSEL_MASK 0x3
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/* CFG Reserved: [31:7] */
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#define CLK_PLL1STAT_ENABLE (1 << 8)
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#define CLK_PLL1STAT_CONNECT (1 << 9)
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#define CLK_PLL1STAT_PLOCK (1 << 10)
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/* STAT Reserved: [31:11] */
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/* CLK_USBCLKCFG Values */
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#define CLK_USBCLKCFG_DIV6 0x5
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#define CLK_USBCLKCFG_DIV8 0x7
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#define CLK_USBCLKCFG_DIV10 0x9
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/* CLK_PCLKSEL0 and CLK_PCLKSEL1 Values */
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#define CLK_PCLKSEL_DIV4 0x00
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#define CLK_PCLKSEL_DIV1 0x01
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#define CLK_PCLKSEL_DIV2 0x02
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#define CLK_PCLKSEL_DIV8 0x03
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#define CLK_PCLKSEL0_WDT_SHIFT 0
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#define CLK_PCLKSEL0_TIMER0_SHIFT 2
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#define CLK_PCLKSEL0_TIMER1_SHIFT 4
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#define CLK_PCLKSEL0_UART0_SHIFT 6
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#define CLK_PCLKSEL0_UART1_SHIFT 8
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/* Reserved: [11:10]*/
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#define CLK_PCLKSEL0_PWM1_SHIFT 12
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#define CLK_PCLKSEL0_I2C0_SHIFT 14
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#define CLK_PCLKSEL0_SPI_SHIFT 16
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/* Reserved: [19:18]*/
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#define CLK_PCLKSEL0_SSP1_SHIFT 20
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#define CLK_PCLKSEL0_DAC_SHIFT 22
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#define CLK_PCLKSEL0_ADC_SHIFT 24
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#define CLK_PCLKSEL0_CAN1_SHIFT 26
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#define CLK_PCLKSEL0_CAN2_SHIFT 28
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#define CLK_PCLKSEL0_ACF_SHIFT 30
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#define CLK_PCLKSEL1_QEI_SHIFT 0
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#define CLK_PCLKSEL1_GPIOINT_SHIFT 2
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#define CLK_PCLKSEL1_PCB_SHIFT 4
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#define CLK_PCLKSEL1_I2C1_SHIFT 6
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/* Reserved: [9:8]*/
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#define CLK_PCLKSEL1_SSP0_SHIFT 10
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#define CLK_PCLKSEL1_TIMER2_SHIFT 12
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#define CLK_PCLKSEL1_TIMER3_SHIFT 14
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#define CLK_PCLKSEL1_UART2_SHIFT 16
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#define CLK_PCLKSEL1_UART3_SHIFT 18
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#define CLK_PCLKSEL1_I2C2_SHIFT 20
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#define CLK_PCLKSEL1_I2S_SHIFT 22
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/* Reserved: [25:24]*/
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#define CLK_PCLKSEL1_RIT_SHIFT 26
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#define CLK_PCLKSEL1_SYSCON_SHIFT 28
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#define CLK_PCLKSEL1_MCPWM_SHIFT 30
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/* CLK_CLKOUTCFG Values */
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#define CLK_CLKOUTCFG_SEL_CPU 0x00
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#define CLK_CLKOUTCFG_SEL_MAIN 0x01
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#define CLK_CLKOUTCFG_SEL_IRC 0x02
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#define CLK_CLKOUTCFG_SEL_USB 0x03
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#define CLK_CLKOUTCFG_SEL_RTC 0x04
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#define CLK_CLKOUTCFG_DIV_SHIFT 4
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#define CLK_CLKOUTCFG_ENABLE (1 << 8)
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#define CLK_CLKOUTCFG_ENABLE (1 << 9)
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/* Reserved: [31:10]*/
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#endif
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