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Make examples/other make use of new clock setup.

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This commit is contained in:
Thomas Otto 2010-05-02 20:28:51 +02:00
parent 4f272b4ad4
commit ffcf53ef00
6 changed files with 6 additions and 218 deletions
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43
examples/other/adc_temperature_sensor/adc.c
View File

@ -23,47 +23,6 @@
#include <libopenstm32/usart.h>
#include <libopenstm32/adc.h>
/* Set STM32 to 72 MHz. HSE 16MHz */
void clock_setup(void)
{
/* enable Internal High Speed Oscillator */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
/* enable External High Speed Oscillator 16MHz */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK);
/* set prescalers for ADC, ABP1, ABP2... make this before touching the PLL */
rcc_set_hpre(HPRE_SYSCLK_NODIV); //prescales the AHB clock from the SYSCLK
rcc_set_adcpre(ADCPRE_PLCK2_DIV6); //prescales the ADC from the APB2 clock; max 14MHz
rcc_set_ppre1(PPRE1_HCLK_DIV2); //prescales the APB1 from the AHB clock; max 36MHz
rcc_set_ppre2(PPRE2_HCLK_NODIV); //prescales the APB2 from the AHB clock; max 72MHz
/* sysclk should run with 72MHz -> 2 Waitstates ; choose 0WS from 0-24MHz, 1WS from 24-48MHz, 2WS from 48-72MHz */
flash_set_ws(FLASH_LATENCY_2WS);
/* Set the PLL multiplication factor to 9. -> 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz */
rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
/* Select HSI as PLL source. */
rcc_set_pll_source(PLLSRC_HSE_CLK);
/* divide external frequency by 2 before entering pll (only valid/needed for HSE) */
rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
}
void usart_setup(void)
{
/* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */
@ -150,7 +109,7 @@ int main(void)
u8 channel_array[16];
u16 temperature;
clock_setup();
rcc_clock_setup_in_hse_16mhz_out_72mhz();
gpio_setup();
usart_setup();
adc_setup();

43
examples/other/dma_mem2mem/dma.c
View File

@ -23,47 +23,6 @@
#include <libopenstm32/usart.h>
#include <libopenstm32/dma.h>
/* Set STM32 to 72 MHz. HSE 16MHz */
void clock_setup(void)
{
/* enable Internal High Speed Oscillator */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
/* enable External High Speed Oscillator 16MHz */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK);
/* set prescalers for ADC, ABP1, ABP2... make this before touching the PLL */
rcc_set_hpre(HPRE_SYSCLK_NODIV); //prescales the AHB clock from the SYSCLK
rcc_set_adcpre(ADCPRE_PLCK2_DIV6); //prescales the ADC from the APB2 clock; max 14MHz
rcc_set_ppre1(PPRE1_HCLK_DIV2); //prescales the APB1 from the AHB clock; max 36MHz
rcc_set_ppre2(PPRE2_HCLK_NODIV); //prescales the APB2 from the AHB clock; max 72MHz
/* sysclk should run with 72MHz -> 2 Waitstates ; choose 0WS from 0-24MHz, 1WS from 24-48MHz, 2WS from 48-72MHz */
flash_set_ws(FLASH_LATENCY_2WS);
/* Set the PLL multiplication factor to 9. -> 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz */
rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
/* Select HSI as PLL source. */
rcc_set_pll_source(PLLSRC_HSE_CLK);
/* divide external frequency by 2 before entering pll (only valid/needed for HSE) */
rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
}
void usart_setup(void)
{
/* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */
@ -113,7 +72,7 @@ int main(void)
char s1[20] = "Hello STM MEM2MEM\r\n";
char s2[20];
clock_setup();
rcc_clock_setup_in_hse_16mhz_out_72mhz();
gpio_setup();
usart_setup();

43
examples/other/dogm128/main.c
View File

@ -26,47 +26,6 @@
#include <libopenstm32/spi.h>
#include "./dogm128.h"
/* Set STM32 to 72 MHz. HSE 16MHz */
void clock_setup(void)
{
/* enable Internal High Speed Oscillator */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
/* enable External High Speed Oscillator 16MHz */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK);
/* set prescalers for ADC, ABP1, ABP2... make this before touching the PLL */
rcc_set_hpre(HPRE_SYSCLK_NODIV); //prescales the AHB clock from the SYSCLK
rcc_set_adcpre(ADCPRE_PLCK2_DIV6); //prescales the ADC from the APB2 clock; max 14MHz
rcc_set_ppre1(PPRE1_HCLK_DIV2); //prescales the APB1 from the AHB clock; max 36MHz
rcc_set_ppre2(PPRE2_HCLK_NODIV); //prescales the APB2 from the AHB clock; max 72MHz
/* sysclk should run with 72MHz -> 2 Waitstates ; choose 0WS from 0-24MHz, 1WS from 24-48MHz, 2WS from 48-72MHz */
flash_set_ws(FLASH_LATENCY_2WS);
/* Set the PLL multiplication factor to 9. -> 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz */
rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
/* Select HSI as PLL source. */
rcc_set_pll_source(PLLSRC_HSE_CLK);
/* divide external frequency by 2 before entering pll (only valid/needed for HSE) */
rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
}
void gpio_setup(void)
{
/* Enable GPIOB clock. */
@ -116,7 +75,7 @@ void spi_setup()
int main(void)
{
clock_setup();
rcc_clock_setup_in_hse_16mhz_out_72mhz();
gpio_setup();
spi_setup();

8
examples/other/i2c_stts75_sensor/i2c_stts75_sensor.c
View File

@ -24,12 +24,6 @@
#include <libopenstm32/i2c.h>
#include "stts75.h"
/* Set STM32 to 72 MHz. */
void clock_setup(void)
{
rcc_clock_setup_in_hse_8mhz_out_72mhz();
}
void usart_setup(void)
{
/* Enable clocks for GPIO port A (for GPIO_USART1_TX) and USART1. */
@ -113,7 +107,7 @@ int main(void)
int i = 0;
u16 temperature;
clock_setup();
rcc_clock_setup_in_hse_16mhz_out_72mhz();
gpio_setup();
usart_setup();
i2c_setup();

43
examples/other/systick/systick.c
View File

@ -25,47 +25,6 @@
u32 temp32;
/* Set STM32 to 72 MHz. HSE 16MHz */
void clock_setup(void)
{
/* enable Internal High Speed Oscillator */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
/* enable External High Speed Oscillator 16MHz */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK);
/* set prescalers for ADC, ABP1, ABP2... make this before touching the PLL */
rcc_set_hpre(HPRE_SYSCLK_NODIV); //prescales the AHB clock from the SYSCLK
rcc_set_adcpre(ADCPRE_PLCK2_DIV6); //prescales the ADC from the APB2 clock; max 14MHz
rcc_set_ppre1(PPRE1_HCLK_DIV2); //prescales the APB1 from the AHB clock; max 36MHz
rcc_set_ppre2(PPRE2_HCLK_NODIV); //prescales the APB2 from the AHB clock; max 72MHz
/* sysclk should run with 72MHz -> 2 Waitstates ; choose 0WS from 0-24MHz, 1WS from 24-48MHz, 2WS from 48-72MHz */
flash_set_ws(FLASH_LATENCY_2WS);
/* Set the PLL multiplication factor to 9. -> 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz */
rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
/* Select HSI as PLL source. */
rcc_set_pll_source(PLLSRC_HSE_CLK);
/* divide external frequency by 2 before entering pll (only valid/needed for HSE) */
rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
}
void gpio_setup(void)
{
/* Enable GPIOB clock. */
@ -91,7 +50,7 @@ void sys_tick_handler()
int main(void)
{
clock_setup();
rcc_clock_setup_in_hse_16mhz_out_72mhz();
gpio_setup();
gpio_clear(GPIOB, GPIO7); /* LED1 on */

44
examples/other/timer_interrupt/timer.c
View File

@ -20,51 +20,9 @@
#include <libopenstm32/rcc.h>
#include <libopenstm32/flash.h>
#include <libopenstm32/gpio.h>
#include <libopenstm32/usart.h>
#include <libopenstm32/timer.h>
#include <libopenstm32/nvic.h>
/* Set STM32 to 72 MHz. HSE 16MHz */
void clock_setup(void)
{
/* enable Internal High Speed Oscillator */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
/* enable External High Speed Oscillator 16MHz */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK);
/* set prescalers for ADC, ABP1, ABP2... make this before touching the PLL */
rcc_set_hpre(HPRE_SYSCLK_NODIV); //prescales the AHB clock from the SYSCLK
rcc_set_adcpre(ADCPRE_PLCK2_DIV6); //prescales the ADC from the APB2 clock; max 14MHz
rcc_set_ppre1(PPRE1_HCLK_DIV2); //prescales the APB1 from the AHB clock; max 36MHz
rcc_set_ppre2(PPRE2_HCLK_NODIV); //prescales the APB2 from the AHB clock; max 72MHz
/* sysclk should run with 72MHz -> 2 Waitstates ; choose 0WS from 0-24MHz, 1WS from 24-48MHz, 2WS from 48-72MHz */
flash_set_ws(FLASH_LATENCY_2WS);
/* Set the PLL multiplication factor to 9. -> 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz */
rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
/* Select HSI as PLL source. */
rcc_set_pll_source(PLLSRC_HSE_CLK);
/* divide external frequency by 2 before entering pll (only valid/needed for HSE) */
rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
}
void gpio_setup(void)
{
/* Enable GPIOB clock. */
@ -95,7 +53,7 @@ void tim2_isr()
int main(void)
{
clock_setup();
rcc_clock_setup_in_hse_16mhz_out_72mhz();
gpio_setup();
nvic_setup();