Stoyan Shopov
e318f884bf
Change the type of 'cortexm_wait_timeout' to unsigned.
...
It makes sense that the timeout value is unsigned, it also
resolves build errors on some platforms.
2020-12-04 11:44:50 +01:00
Uwe Bonnes
653d486ee2
cortexm: Store CPUID in target structure.
2020-11-27 22:26:48 +01:00
Uwe Bonnes
159196c2ad
Cortexm: Remove forced_halt.
2020-10-07 20:11:33 +02:00
Fredrik Ahlberg
fcd945a529
cortexm: Read CPUID to identify core version
2020-07-12 12:08:22 +02:00
Uwe Bonnes
a0e42e229b
Make more things static.
...
No functional change intendend.
2020-03-26 18:44:19 +01:00
UweBonnes
6663da7ff5
cortexm.c: Fix DWT Mask ( #516 )
...
See #513
2019-09-04 13:28:55 +02:00
Uwe Bonnes
525b90d4e5
cortexm: Only force halt before probe() if probe was forced.
2019-01-07 13:22:01 +13:00
Gareth McMullin
b2defad844
Merge pull request #356 from UweBonnes/probe_halted
...
Probe halted
2018-06-21 10:06:56 -07:00
Uwe Bonnes
54f73858f9
Provide a target function to write with given size.
2018-06-16 13:30:08 +02:00
Uwe Bonnes
17b817f37b
cortexm: Allow to set timeout to wait for halt.
...
This allows to gain access to devices spending long time in WFI without
the need for a reset, at the expense of possible long waiting times.
Using Reset means loosing the device runtime context.
2018-06-13 14:03:50 +02:00
Gareth McMullin
c53a12bfd1
cortexm: Better cache support for Cortex-M7
...
- On probe, read CTR for cache presence and minimum line length
- Make D-Cache clean a function
- Clean before memory reads
- Clean and invalidate before memory writes
- Flush all I-Cache before resume
2017-10-12 09:26:01 +13:00
Nick Downing
0e5b3ab00e
Make Cortex M driver write DCCIMVAC (Data cache clean and invalidate by address to the PoC=Point of Coherency) prior to reading or writing each 32 bytes of RAM
2017-10-12 08:41:58 +13:00
Gareth McMullin
b494279fe5
Move target files into separate directory.
2016-07-13 08:31:09 +12:00
