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237 Commits

Author SHA1 Message Date
Uwe Bonnes
2065c70888 adiv5: Split PRIx64 into two PRIx32 as nanolib does not support PRIx64. 2020-03-10 10:56:42 +01:00
Uwe Bonnes
75186f7d50 ADIv5: More CoreSight device decoding: 
- MTB-M0+ (Simple Execution  Trace)
- M33: Devices need finer decoding (DEVTYPE at offset 0xfcc)
 2020-03-08 22:37:59 +01:00
Uwe Bonnes
919d9320fd Remove unrelated files. 2020-03-06 19:33:20 +01:00
Uwe Bonnes
288620551f adiv5: Print out SYSROM PIDR. 
We need to know more about what devices indicate proper PIDR and what
devices fail to do so.
 2020-03-04 19:02:07 +01:00
Uwe Bonnes
8c959defca efm32: Make local functions static. 2020-03-04 18:44:40 +01:00
Uwe Bonnes
470c8e8cf1 target_flash_erase: Do not crash when requesting erase of unavailable flash. 
Allow to erase from command line.
 2019-12-13 14:59:42 +01:00
Uwe Bonnes
ab396f9745 Allow %z specifier in windows builds. Supercedes #562. 2019-12-08 16:43:19 +01:00
Uwe Bonnes
1bef51e145 adiv5: Abort scanning APs after 8 void APs. 2019-12-08 16:43:19 +01:00
Uwe Bonnes
bdd76de517 Erase: Fix endless erase when erase-area did not end on (page|block) boarder. 2019-12-08 16:43:19 +01:00
Uwe Bonnes
25d24e5c34 efm32: Allow to compile with -Og. 2019-12-08 16:43:19 +01:00
Richard Meadows
5943552a6b [efm32] Probe for the EFM32 Authentication Access Port (AAP) 
Supported functionality through this AP:
* Issuing a DEVICEERASE command
 2019-12-08 16:21:02 +01:00
Richard Meadows
260fc88d8f [efm32] Add command to set and print bootloader enable status 
This is a bit in the Lock Bit (LB) flash page, so it can only be
cleared by this routine
 2019-12-08 16:17:02 +01:00
Richard Meadows
7f0d5febc3 [efm32] Print MSC Interrupt Flags to DEBUG after each flash write 2019-12-08 16:16:55 +01:00
Richard Meadows
e85df763b7 [efm32] add new devices PG12B, JG12B, GG11B, TG11B, GG12B 
Rework MSC layout check
 2019-12-08 15:55:12 +01:00
UweBonnes
f89542c79f
Merge pull request #203 from dlaw/master 
Add LPC11xx command to read out unique ID from target. Restore Ram and registers after call.
 2019-12-08 15:45:49 +01:00
Artur Maciuszonek
8a07f44435 Add support for the kinetis KL16Zxx devices. Tested on KL16Z128VFM4 custom hardware 2019-11-21 20:37:13 +01:00
Uwe Bonnes
e7e34600a4 lpc11: Only print Idcode if not zero and not yet handled. 
Otherwise for all Cortex-M not yet handled this LPC messages appears.
 2019-11-17 13:24:39 +01:00
Ken Healy
9198c951bb Reduce flash space required for SAM D51/E5x driver 
* Reuse functions that are common with the SAM D1x/D2x driver
* Only include the mbist and write8/16/32 user commands if
  SAMX5X_EXTRA_CMDS is defined
 2019-11-17 12:45:49 +01:00
Ken Healy
d3c330ea1a Fix issues with Travis CI build 
It appears the Travis version of gcc-arm-none-eabi doesn't allow the %x
printf format specifier for size_t arguments, in contrast with the
version I'm running on Ubuntu 18.04 (15:6.3.1+svn253039-1build1).
 2019-11-17 12:45:49 +01:00
Ken Healy
26216beaab Microchip SAM D51 / E5x support 
Adds a target driver for Microchip SAM D51 / E5x family.

Tested on SAMD51G19A and SAMD51J19A. According to the datasheet, the
D51 / E5x family share the same core feature set, differing only in the
addition of CAN (E51) or ethernet controllers (E53/54). All members of
the family should be equivalent from a debug and programming perspective.
 2019-11-17 12:45:49 +01:00
Kirill Zhumarin
28f0ced97e Support NXP LPC1343 2019-11-09 18:47:07 +01:00
dpslwk
67f9d26644 samd: Add support for L21 & L22 (PR #345) 2019-11-09 13:59:37 +01:00
Uwe Bonnes
b9249fe104 adiv5: Activate DP reset sequence, guarded with timeouts. 
While not working on most STM32, it succeeds on STM32G474.
Thanks to Dave Marples <dave@marples.net>
 2019-10-20 22:15:28 +02:00
Thomas Bénéteau
4a8cba0e9c Add support for LPC1114/333 (LPC1100XL series) 
This is not given in the user manual but the register immediately
following DEVICE_ID does apparently contain the correct part ID.
 2019-10-13 13:01:19 +02:00
Ken Healy
5c805c7d35 Fix buffer overflow in adiv5_component_probe() 2019-10-12 11:44:08 +02:00
Uwe Bonnes
0ae7cea1ae Add LPC84 from UM11029, Rev. 1.4, tested on LPC845 Breakout board. 2019-10-08 18:17:43 +02:00
Uwe Bonnes
1cf0b8ac13 Make all arguments for all commands (struct *t, int argc, const char **argv). 
-Wall on gcc8 otherwise warns without -Wno-cast-function-type but older
GCCs/CLang choke on that argument:
error: unknown warning option '-Wno-cast-function-type'; did you mean
 '-Wno-bad-function-cast'? [-Werror,-Wunknown-warning-option]

This adds 24 byte to the binary, as some functions are now called with
additional dummy arguments:
"Pushing and popping garbage to keep the system happy"
 2019-09-29 12:44:55 +02:00
Uwe Bonnes
f010a567bd adiv5: Reject APs duplicating last AP. 
Seen with TM4C129 on black MSP432R401 Launchpad. Scanning of APs is aborted,
so valid APs after duplicated APs are ignored.
 2019-09-29 12:44:37 +02:00
Uwe Bonnes
fae2966b72 Target: Default to nop-function() for all exported target functions. 
Fixes #522.
 2019-09-23 17:42:29 +02:00
UweBonnes
609e6b135d
nrf51: Add nop_function as halt_poll. (#517) 
Otherwise "tar  ext ...; mon s; att 2; quit", start new gdb "tar ext ..."
crashes, at least on pc-hosted platforms.
 2019-09-04 13:50:13 +02:00
UweBonnes
6663da7ff5
cortexm.c: Fix DWT Mask (#516) 
See #513
 2019-09-04 13:28:55 +02:00
UweBonnes
00937348b3
Fixes to compile "make ENABLE_DEBUG=1 all_platforms" (#515) 2019-09-04 13:09:43 +02:00
Gareth McMullin
e6504e149b cortexm: Implement single register read/write 2019-09-01 20:38:38 +02:00
Gareth McMullin
7bcf7f4924 cortexa: Implement single register read/write 2019-09-01 20:38:38 +02:00
Gareth McMullin
20cad17ce3 target: Implement generic multi-register read/write 2019-09-01 20:38:38 +02:00
Gareth McMullin
9f4cf4124e target: Add new methods for read/write individual regs. 2019-09-01 20:38:38 +02:00
Uwe Bonnes
d39dc34382 pc-stlinkv2: Fix reg_read|write 
- Fix wrong placed brace in cortexm_regs_write()
- Start writing with r0
- With register read, save only registers listed
 2019-09-01 12:11:37 +02:00
Uwe Bonnes
aef055bb6f adiv5: If setup AP0 fails, fail immediate. 2019-08-31 11:20:17 +02:00
Uwe Bonnes
6bf4fd3598 pc-stlinkv2: CPU register read and write must be done with the AP set. 
FIXME: Writing CPU registers on M4 of STM32H745 seems not to work.
 2019-08-27 15:13:15 +02:00
Sylvain Munaut
4289788e0b src: Replace sprintf with snprintf 
snprintf is needed anyway, that's one less function to have :p
And it's bad practice anyway.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-08-05 15:43:33 +02:00
Sylvain Munaut
1d4152a36f target: Make sure variant_string is consistent in size 
It's a global symbol and LTO will complain if the one in this file and
the one in EFM32 target are inconsistent.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2019-08-05 15:42:29 +02:00
Uwe Bonnes
e29f2b4fb9 jtag/swd: Rename defines/make variables to allow removal of weak attribute 
jtagtap.c is libopencm3 generic. Move to common.
 2019-07-18 20:54:10 +02:00
Uwe Bonnes
067956266c Adiv5: Remove weak attribute to ease windows compile. 2019-07-18 18:16:19 +02:00
Uwe Bonnes
9e898cc4b8 adiv5: Add more coresight part numbers found on STM32MP157c-DK2 (#492). 
Only print corename if not NULL.
 2019-07-18 17:39:48 +02:00
Uwe Bonnes
dd3cb193f3 Indicate the Core in the Target list. 2019-07-17 17:38:21 +02:00
Uwe Bonnes
c44cb904b0 adiv5.c: Format debug output more tense. 2019-07-17 17:38:21 +02:00
Uwe Bonnes
634c07c432 adiv5: Add TSGEN. 2019-07-17 17:38:21 +02:00
Uwe Bonnes
9ed26645d3 Add pc_stlinkv2 platform, running on host, talking to original StlinkV2/3. 
Stlink firmware needs to be recent.
 2019-07-17 17:38:01 +02:00
Uwe Bonnes
32d2b2c4bf jtag: Move device list to it's own file to allow reuse. 2019-07-17 17:26:00 +02:00
Uwe Bonnes
bd530c8951 adiv5.c: Make functions weak where high level platforms may implement different. 2019-07-17 17:26:00 +02:00