newbrain
8de1b45c85
Kinetis KE04: Flash and debug support
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Support for Kinetis KE04 8KiB, 64KiB and 128KiB variants in nxpke04.c
Target monitor commands for sector and mass erase.
Changes to kinetis.c MDM-AP target to support KE04.
Only KE04Z8 tested in HW.
2019-02-17 22:48:23 +01:00
Carl
02c1934c03
Added ability to lock and unlock boot rom for samd controllers
2019-02-13 16:33:07 -08:00
Uwe Bonnes
a6b75bb4ef
Makefile: Add -Wnocast-function-type for compilation on gcc8.
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Older GCC versions do not warn for disabled warnings they do not know yet.
This is needed to compile with gcc8.
2019-01-16 23:17:17 +01:00
Richard Meadows
0b28232f72
[efm32] Assume Device Identification (DI) version 1 if we don't know the OUI ( #402 )
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* [efm32] Assume Device Identification (DI) version 1 if we don't know the OUI
Silabs are using some additional OUIs we don't know about. Reported in issue #389
These should use a DI version 1 layout, so assume version 1 layout for OUIs we don't
know. However do print a notice about this on DEBUG() as suggested by @UweBonnes
The IDCODE value is sufficient to make a positive identification of an EFM32 device.
See AN0062 Section 2.2. Therefore accepting any OUI is reasonable behaviour.
Additionally the part familiy is checked, and the target rejected if not in the
`efm32_devices` table. This commit makes that rejection explicit, although it does
not change the logical behaviour here.
Note that the important registers (part number, part family, flash size) are at the
same addresses in both layouts anyhow. Currently only `efm32_cmd_serial` and
`efm32_cmd_efm_info` functions use registers that differ between DI versions.
* [efm32] tidy format warning about portability UB
* [efm32] Simplify OUI checking
* Only read the OUI once
* Accept the device even if the OU is unknown, as silabs have been using
a variety of OUIs
* Perform fewer register reads before checking the device family is valid
2019-01-16 09:58:59 +13:00
Uwe Bonnes
7cc02867ae
stm32f4: Fix problems with small flash sizes creating overflow or empty regions.
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Thanks to "DerMeisteRR" for pointing out.
2019-01-09 12:23:49 +01:00
Uwe Bonnes
47fad2bf7f
Add Stm32L41x.
2019-01-09 12:23:49 +01:00
Uwe Bonnes
f0c6e2bbd2
Add STM32G07x.
2019-01-09 12:23:49 +01:00
Uwe Bonnes
0793dac2cf
libftdi: Allow to compile with mingw and cygwin and use recent libftdi1.
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Tested with x86_64-w64-mingw32-gcc-8.2.0 and cygwin gcc (GCC) 7.3.0.
Use libftdi1 unconditionally.
Try to convice github travis to use libftdi1.
Remove unportable "uint ". Thanks to jacereda for pointing out in #400 .
2019-01-07 15:31:57 +01:00
Ingmar Jager
3f0c9ccee1
Fix support for LPC1115 and LPC1115XL devices ( #415 )
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* Add support for LPC11U3X devices.
The DeviceID register has a different address from the LPC11XX devices.
But it is shared with the LPC8XX family.
* Fix support for LPC1115 and LPC1115XL devices
* Fix whitespace
2019-01-07 13:34:00 +13:00
Josh Robson Chase
02b9d5f1ac
Add delay to cortexm_reset
2019-01-07 13:32:17 +13:00
Josh Robson Chase
d7e2923990
Debug on stm32f1_flash_erase errors
2019-01-07 13:32:17 +13:00
Uwe Bonnes
6df793dbf0
Revert "Allow to specificy if SRST is asserted and when it is released."
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This reverts commit 44fc24e0e747293fa05b62ed7439501553829b0b.
2019-01-07 13:22:01 +13:00
Uwe Bonnes
9ce05ae67b
stm32h7/f7: Store DBGMCU_CR on attach() and restore on detach().
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On STM32[FH]7, DBG_SLEEP must be set for debugging.
2019-01-07 13:22:01 +13:00
Uwe Bonnes
8d6092b73f
cortexm_forced_halt: Only release SRST after "Halt on reset" command.
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This should make life easier if program remaps JTAG/SWD pins so that
with program running, JTAG/SWD access is impossible.
2019-01-07 13:22:01 +13:00
Uwe Bonnes
3ebf049424
cortexm: Only force halt before probe if idcode is unknown and ROM TABLE unreadable.
2019-01-07 13:22:01 +13:00
Uwe Bonnes
6633f74d95
stm32h7/f7: Write DBGMCU_CR only on attach.
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Split probe/attach for STM32H7.
2019-01-07 13:22:01 +13:00
Uwe Bonnes
8575d3e7a6
stm32f7/h7: Use the DPv2 provided idcode for MCU identification.
2019-01-07 13:22:01 +13:00
Uwe Bonnes
525b90d4e5
cortexm: Only force halt before probe() if probe was forced.
2019-01-07 13:22:01 +13:00
Uwe Bonnes
da75acf015
adiv5: Only force cortexm_probe() once.
2019-01-07 13:22:01 +13:00
Uwe Bonnes
489f24584b
adiv5: Read TARGETID on DPv2 devices.
2019-01-07 13:22:01 +13:00
Uwe Bonnes
cde7726b87
cortexm: detach still needs extra cycles.
2019-01-07 13:22:01 +13:00
Ingmar Jager
14bedcc441
Add support for LPC11U3X devices.
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The DeviceID register has a different address from the LPC11XX devices.
But it is shared with the LPC8XX family.
2018-10-04 08:53:05 -07:00
Benjamin Vernoux
771d81a5f0
Fix link for windows_dfu_util
2018-10-03 15:20:09 -07:00
Uwe Bonnes
d8b01ff61f
swlink: Enable UART2 for SWO.
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Stlink on STM8S-Disco needs additional wiring for SWO.
2018-10-03 15:19:33 -07:00
Uwe Bonnes
7cafc44bd9
swlink: Allow to enable debug on second VCOM.
2018-10-03 15:19:33 -07:00
Uwe Bonnes
0d246fb31a
swlink: Measure voltage on VDD pin of Stlink/Stm8s.
2018-10-03 15:19:33 -07:00
Uwe Bonnes
184ef991bf
swlink: Handle LED.
2018-10-03 15:19:33 -07:00
Uwe Bonnes
06272e0a59
swlink: Implement dfu_upgrade.
2018-10-03 15:19:33 -07:00
Uwe Bonnes
530d1e5c28
swlink: Handle force boot on bluepill.
2018-10-03 15:19:33 -07:00
Uwe Bonnes
b744d8b0c9
swlink: Implement NRST.
2018-10-03 15:19:33 -07:00
Uwe Bonnes
1263d185a6
swlink: Distinguish between Stlink on STM8-Disco and "blue pill".
2018-10-03 15:19:33 -07:00
Mark Rages
91dd879dac
Another nRF52 ID.
2018-09-13 16:18:29 -06:00
Gareth McMullin
3a598a0cf3
Merge pull request #384 from rikvdh/feature/readable-reset-stlink
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Change the ST-Link SRST reset function
2018-09-07 08:13:48 +12:00
Uwe Bonnes
f5cf6d4497
adiv5_swdp: Add extra idle cycles with write transactions.
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These extra cycles are needed by some CPU, e.g. STM32L0x1 to cross the SWCLK
/HCLK domains. Revert insufficient #373 also tackling that problem.
Thanks to Thorsten von Eicken for pointing out.
2018-09-06 17:29:20 +02:00
Rik van der Heijden
95053b3b4e
Change the ST-Link SRST function to use libopencm3 helper functions and fix waiting for the pin-state, change init to use the SRST function for reset de-assertion
2018-09-05 20:28:02 +02:00
Rik van der Heijden
f39701c4c8
Move the LPC17xx probe function down since it performs an IAP call which can hang when performed on other devices than a LPC17xx
2018-09-05 17:40:02 +02:00
Gareth McMullin
c5c0783337
Merge pull request #378 from markrages/nordic_unlock
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Add extra port for mass erasing / unprotecting nRF52 with APPROTECT set.
2018-07-28 14:56:03 +12:00
Mark Rages
d0a8ce0819
Add extra port for mass erasing / unprotecting nRF52 with APPROTECT set.
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Mostly copied from the equivalent in kinetis.c and
https://devzone.nordicsemi.com/f/nordic-q-a/12484/approtect-and-dap/47301
2018-07-27 16:07:19 -06:00
Gareth McMullin
6fd3ede5c7
Merge pull request #377 from markrages/add_id_2
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Another chip ID for Nordic nRF52832.
2018-07-28 09:53:00 +12:00
Mark Rages
cb8596b0b2
Another chip ID for Nordic nRF52832.
2018-07-27 15:09:14 -06:00
Uwe Bonnes
5918608156
STM32F7: Debug does not work with WFI without DBG_SLEEP
2018-07-27 10:59:54 +02:00
Uwe Bonnes
2c1c913213
adiv5.c: Add units found on M7.
2018-07-27 10:59:54 +02:00
Uwe Bonnes
f234074099
stm32h7: Start of support.
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Implement probe, memory map, erase, write, uid, crc, parallelism.
2018-07-27 10:59:54 +02:00
Gareth McMullin
a988bba035
Merge pull request #372 from richardeoin/efm32-1
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[efm32] Add support for EFM32 devices with different DI and MSC layouts
2018-07-27 11:41:58 +12:00
Gareth McMullin
d7b173ab39
Merge pull request #310 from UweBonnes/stm32l4r
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arget/stm32l4.c: Add stm32l4r series and clean up.
2018-07-27 10:32:00 +12:00
Mike Walters
b4dc666aca
Add nRF52 QIAA C0
2018-07-26 23:13:38 +01:00
Uwe Bonnes
4a312c7697
target/stm32l4.c: Add stm32l4r series and clean up.
2018-07-22 15:44:00 +02:00
Uwe Bonnes
7034d0bb94
stm32l4: Option byte loader must be started with flash unlocked!
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Warn user that device will loose connection.
2018-07-22 15:44:00 +02:00
Uwe Bonnes
83f9655f6e
stm32l4: Fix wrong default for WRP2A option halfword.
2018-07-22 15:44:00 +02:00
Uwe Bonnes
139707c5c0
cortexm/detach: Add a dummy transaction after cleaning DHCSR.
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This replaces the seemingly superflous swdptap_seq_out() at
the end of adiv5_swdp_low_access() needed to continue after detach.
2018-07-19 10:57:41 +02:00