Richard Meadows
98faaceb70
[efm32] Add support for EFM32 devices with different DI and MSC layouts
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* DI layout is identified by attempting to read OUI from both layouts
* MSC address is passed to flashstub in r3
Retested EZR32LG230 (EZR Leopard Gecko M3)
Tested EFR32BG13P532F512GM32 (EFR Blue Gecko)
Achieves aims of PR #264 (I think) Thanks to @dholth and @ryankurte for inspiration
Fixes Issue #226
2018-07-16 20:18:36 +00:00
Antti Louko
59d6eca8f0
Fixes option erase for STM32F070x6 STM32F070xB STM32F030xC
2018-07-10 18:44:05 +03:00
Gareth McMullin
c5713ea8d3
Merge pull request #366 from UweBonnes/f7_fix
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stm32f4.c: F76x also has large sector by default.
2018-07-07 13:03:14 +12:00
Gareth McMullin
1b51c4961e
Merge pull request #363 from korken89/master
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Removed debug bits for F4/F7 target, same as all other MCUs now
2018-07-07 13:01:05 +12:00
Uwe Bonnes
50514ccc31
stm32f4.c: F76x also has large sector by default.
2018-07-05 13:29:43 +02:00
Emil Fresk
5e8c8cae10
Removed debug bits for F4/F7 target, same as all other MCUs now
2018-06-28 16:31:34 +02:00
Uwe Bonnes
5548d54626
common/swdptap: some clean up.
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Remove superfluous transaction.
Use native variable size.
2018-06-26 19:50:14 +02:00
Uwe Bonnes
7e3fe352ad
adiv5_swdp.c: Use swdptap_seq_out for initialiation sequence.
2018-06-26 19:50:14 +02:00
Gareth McMullin
b2defad844
Merge pull request #356 from UweBonnes/probe_halted
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Probe halted
2018-06-21 10:06:56 -07:00
Uwe Bonnes
b59bbac0b2
stm32l4: Use buffered direct write to flash.
2018-06-16 13:30:53 +02:00
Uwe Bonnes
891d6de8eb
stm32f1.c: Use buffered direct write to flash with half word access.
2018-06-16 13:30:53 +02:00
Uwe Bonnes
f1752c7a1a
stm32f4: Allow DWORD parallelism.
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Needs external VPP!
2018-06-16 13:30:53 +02:00
Uwe Bonnes
15312eb86c
stm32f4: Honor parallelism also for erase.
2018-06-16 13:30:53 +02:00
Uwe Bonnes
bfeb6f0db9
stm32f4: Use buffered direct flash write with choosen size.
2018-06-16 13:30:53 +02:00
Uwe Bonnes
54f73858f9
Provide a target function to write with given size.
2018-06-16 13:30:08 +02:00
Uwe Bonnes
17b817f37b
cortexm: Allow to set timeout to wait for halt.
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This allows to gain access to devices spending long time in WFI without
the need for a reset, at the expense of possible long waiting times.
Using Reset means loosing the device runtime context.
2018-06-13 14:03:50 +02:00
Uwe Bonnes
9e365a58f7
Cortex-M: Try harder to halt devices in WFI.
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E.g. STM32F7 and L0 need multiple C_DEBUG and C_HALT commands to halt
the device.
2018-06-13 14:02:43 +02:00
Uwe Bonnes
66e357d517
Cortex-M: Probe Cortex-M even if ROM table read fails.
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Rom table in some devices (e.g. STM32L0/F7) can not be read while
device is in WFI. The Cortex-M SWD signature is however available.
If we know by that signature, that we have a Cortex-M, force a
probe for Cortex-M devices.
2018-06-13 13:04:17 +02:00
newbrain
ae6f0eadc9
Support for MSP432 TI MCUs ( #353 )
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Introduces flashing and debugging support for Texas Instruments MSP432
series of MCUs
2018-06-07 08:34:21 +12:00
Piotr Esden-Tempski
077e455a94
Setting the driver string on scan.
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This way swdp_scan and jtag_scan commands will show the chip that was
detected instead of the generic STM32F4 string. The generic name is
most confusing when attaching to an STM32F7 target.
2018-06-01 12:46:14 -07:00
Uwe Bonnes
df05d7ce7b
libftdi: Allow device specific port/pin to read SWD bitbanged.
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Gracefully abort swd scan if devices can not do SWD.
Best effort to indicated SWD capability on existing cables and
add descriptions for the cables.
2018-05-30 19:21:03 +02:00
Uwe Bonnes
f3cacba219
libftdi: Flush buffer with detach.
2018-05-30 19:21:03 +02:00
Gareth McMullin
48d232807e
Merge pull request #337 from adamgreig/stm32f4-ram-size
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Update maximum RAM sizes for F4 and F7 devices
2018-04-26 13:38:11 +12:00
Adam Greig
e1cefb2031
Update maximum RAM sizes for F4 and F7 devices
2018-04-24 11:06:07 +01:00
Uwe Bonnes
93f3b14b68
stm32f1(f0): Do not read normal device registers during probe.
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Device may not be halted and memory map setup may fail.
2018-04-23 11:06:08 +12:00
Uwe Bonnes
a0596a0dcc
stm32l4: Build Memory Map during attach.
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Reading target registers while target not halted may fail and result in
invalid memory map.
2018-04-23 11:06:08 +12:00
Uwe Bonnes
5f404cdbc0
Construct memory map on the stack
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The memory map uses 1k of SRAM and is only needed during attach. Release
after use lowers pressure on SRAM.
2018-04-23 10:51:04 +12:00
Gareth McMullin
63967346cd
stm32f4: Don't duplicate resources on reattach.
2018-04-23 10:48:05 +12:00
Gareth McMullin
00decb3718
target: Separate function to free memory map.
2018-04-23 10:48:05 +12:00
Gareth McMullin
1fd2a24c2d
stm32f4: Only construct memory map at attach.
2018-04-23 10:48:05 +12:00
Gareth McMullin
9d7925792f
Merge branch 'master' into always_buffer_flash
2018-04-23 10:40:20 +12:00
Mike Walters
fa62403ee3
nrf51: Add nRF51802 device id. ( #331 )
2018-04-03 10:45:56 +12:00
Gareth McMullin
cfaa5ea963
Merge branch 'korken89-master'
2018-03-27 13:01:06 +13:00
Gareth McMullin
76bfb4929d
Use lowercase register names.
2018-03-27 13:00:39 +13:00
Gareth McMullin
a3f855ce5c
Merge branch 'master' of https://github.com/konsgn/blackmagic into konsgn-master
2018-03-27 08:03:03 +13:00
Christopher Woodall
31965a5bbc
Added support for k64 ( #301 )
2018-03-25 14:43:33 -07:00
Akila Ravihansa Perera
471ce2547c
Added LPC17xx support ( #317 )
2018-03-25 12:53:30 -07:00
Mark Rages
a41d8cb97a
Another nRF52 device id. ( #315 )
2018-03-25 12:37:51 -07:00
Emil Fresk
1ee6d4503e
Update to split 'special' into its sane parts (update from @mubes)
2018-03-24 16:44:59 +01:00
Konsgn
04fbabb299
mkl27 support
2018-01-21 23:43:01 -05:00
konsgn
1fe870b8df
added MKL27<128kB support
2018-01-16 13:23:36 -05:00
Uwe Bonnes
922f857de7
stm32f1.c: Add missing fall through statement needed by GCC7.
2017-12-18 13:56:59 +01:00
Uwe Bonnes
1f3c235205
src/target/stm32f1.c: Add CCM Ram of STM32F303 devices.
2017-12-08 13:39:24 +01:00
Gareth McMullin
048e8447a5
target: Only support buffered flash writes
2017-10-13 08:58:37 +13:00
Gareth McMullin
c53a12bfd1
cortexm: Better cache support for Cortex-M7
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- On probe, read CTR for cache presence and minimum line length
- Make D-Cache clean a function
- Clean before memory reads
- Clean and invalidate before memory writes
- Flush all I-Cache before resume
2017-10-12 09:26:01 +13:00
Nick Downing
0e5b3ab00e
Make Cortex M driver write DCCIMVAC (Data cache clean and invalidate by address to the PoC=Point of Coherency) prior to reading or writing each 32 bytes of RAM
2017-10-12 08:41:58 +13:00
Uwe Bonnes
120a2d9378
target: Fix calculation of erase size.
2017-10-05 22:11:01 +02:00
Uwe Bonnes
a7815fff3d
target.c: No need to split write while still in same flash block.
2017-10-04 21:52:29 +02:00
Uwe Bonnes
25610e5ec5
target: Fix unconsistant use of tmplen.
2017-10-04 21:52:29 +02:00
Uwe Bonnes
0aa47113f3
stm32f4: Fix F4 dual bank OPTCR1 to option byte mapping.
2017-10-02 16:22:14 +02:00