17 Commits

Author SHA1 Message Date
Gareth McMullin
6b49fbe594 Quiet adiv5 probe. 2016-07-13 08:31:09 +12:00
Gareth McMullin
2a5efbc1ac Merge pull request #140 from gsmcmullin/va_translation
cortexa: Virtual address translation and memory access through APB.
2016-06-30 18:23:31 +12:00
Gareth McMullin
4596d88f72 cortexa: Use fast mode for APB mem access and allow byte access. 2016-06-30 17:56:01 +12:00
Gareth McMullin
d16aca9ae0 cortexa: Fall back to APB memory access if no AHB available. 2016-06-29 11:11:27 +12:00
Gareth McMullin
ea9c2a2030 cortexa: Catch and report faults on address translation. 2016-06-29 11:11:27 +12:00
Gareth McMullin
9e2b0a86d7 cortexa: Perform VA translation on memory access. 2016-06-29 11:11:27 +12:00
Gareth McMullin
60c67ee156 cortexa: Flush I-Cache on detach. 2016-06-28 14:35:43 +12:00
Gareth McMullin
6b3c3d3473 cortexa: Add timeout to reset spin. 2016-06-28 14:35:43 +12:00
Gareth McMullin
8b4342394f Overhaul of timeouts so they may be nested. 2016-06-28 14:35:43 +12:00
Gareth McMullin
90c0c28327 cortexa: Redirect read of PC through r0. MCR is unpredictable for r15. 2016-06-23 12:00:04 +12:00
Gareth McMullin
13602c5d85 cortexa: Also assert SRST to reset. 2016-04-20 12:55:12 -07:00
Gareth McMullin
68bf825042 cortexa: Disable interrupts while single stepping. 2016-04-20 11:35:58 -07:00
Gareth McMullin
88bf92ac36 cortexa: Fix write back of PC and CPSR. 2016-04-20 11:35:25 -07:00
Gareth McMullin
0ab878dcd2 cortexa: Add short delay after reset, before reattaching.
Allows the early bootloader to configure the DDR ram.
2016-04-19 13:29:22 -07:00
Gareth McMullin
a2ec877b73 cortexa: Restore cache clean and invalidate on memory writes.
Include a small optimisation of APB access to speed up the process.
2016-04-19 13:24:05 -07:00
Gareth McMullin
49f89cfc95 cortexa: Fix detach.
Also pulls out internal register cache functions from halt/resume.
2016-04-19 13:24:05 -07:00
Gareth McMullin
f6b574e0b0 Cortex-A target support. 2016-04-19 13:24:05 -07:00