349 Commits

Author SHA1 Message Date
fabalthazar
6d6cfd6c98 Comprehensive STM32G03/4/5/6/7/8/B/C driver 2021-03-29 21:42:40 +02:00
Uwe Bonnes
58f153e12b cortexm: Always halt and release reset before romtable scan
Only release from halt once after romtable scan
Should fix #836.
2021-03-26 17:43:11 +01:00
Uwe Bonnes
a025c9a7bd Revert "stm32f1: On ST parts there is no need to read IDCODE again."
Romtable partno is not unique for devices, e.g. in STM32F0
This reverts commit f89b07d892c6034ea68494a72e047b2c437754f7.
2021-03-26 17:35:00 +01:00
Uwe Bonnes
f89b07d892 stm32f1: On ST parts there is no need to read IDCODE again.
IDCODE is already known from the Romtable
Probably this has the same effect as #836
2021-03-12 20:45:34 +01:00
Uwe Bonnes
7859a2aabd adiv5_swd: Factor out creation of packet request. 2021-03-06 13:30:09 +01:00
Uwe Bonnes
cfb784d428 adiv5: Fix comments and debug output 2021-03-05 16:49:19 +01:00
Thiadmer Riemersma
560a046a22 Add support for NXP LPC802, LPC804, LPC832 and LPC834 2021-02-22 19:37:46 +01:00
Uwe Bonnes
0df44e205b ADIv5: Abort Romtable scan also if CIDR0 is invalid after halting #832
STM32WLE5 has the same dual core chip as STM32WL5. For the second
core, the additional AP can be see, but access to e.g. CIDR0 for that
Romtable fails.
Aborting the scan too if again the second read of CIDR0 fails makes
sense anyways!
2021-02-19 18:48:02 +01:00
Uwe Bonnes
c776e7a9a6 swd_scan: Add '-m' as targetid argument to swd_scan to prepare multi-drop.
In a real multi-drop setup, the device to use must be specified.
2021-02-15 17:47:29 +01:00
Uwe Bonnes
8e2f6937d5 hosted: Run target specific monitor commands with -M "command" .
Lists available commands: "blackmagic -M help"
Quote multi argument monitor commands, e.g. STM32F1: blackmagic -M "option help"
2021-02-15 17:47:29 +01:00
Uwe Bonnes
165560edd8 cl_utils: target selection '-n' argument needs optarg.
foreach now returns the number of targets.
2021-02-15 17:47:29 +01:00
Alex Norman
42f590ce0b fixing some memory map errors for stm32h7, PR #821 2020-12-23 20:10:39 +01:00
Sean Cross
2b06f045c4 target: kinetis: add S32K148
This adds support for the NXP S32K148. This is an automotive-grade part
that is derived from the Kinetis line, so it has a very similar
interface to other parts in the family.

Signed-off-by: Sean Cross <sean@xobs.io>
2020-12-16 12:49:23 +01:00
Noah Pendleton
020600aa56 target/lpc546xx: fix lpc546xx flash support (#801)
**Summary**
Modifications to fix flash support on the lpc546xx:

- fix IAP entrypoint to be `0x03000204`, not the value at that address
- add a reset and attach sequence before erasing flash sectors. there's
little documentation around this, but experimentally, erasing sector 0
fails when the ROM bootloader is mapped to it (on reset). stepping the
chip once and attaching is enough to snap the chip out of it, permitting
flash erase on sector 0.
- add a few test commands to the lpc546xx table (read_uid, erase/write
sector, etc).
- write the magic CRC value when writing to sector 0
(`lpc_flash_write_magic_vect`).
- move the lpc546xx probe to before the lpc43xx probe, to prevent
getting the lpc546xx into Lockup when reading an illegal memory location
during lpc43xx probing

Fixes #786.

I don't 100% understand the reset/load sequence of this part, but these
changes are sufficient to program and debug the part now.

I didn't do a detailed analysis of what pyocd (via st-link hardware
adapter) and segger jlink do to handle the same, but both of those
worked without modification, so there's some difference in the
sequence they're using.

**Testing**
Verified I can now successfully erase and write an executable in sector
0 (and other sectors).
Verified the new commands work correctly.
2020-12-12 19:48:05 +01:00
Aaron Lindsay
518529a772 Support GD32E23x 2020-12-12 18:29:30 +01:00
Uwe Bonnes
dd6aadc54d jtag: Add verbosity about devices found. 2020-12-06 15:18:08 +01:00
Stoyan Shopov
e318f884bf Change the type of 'cortexm_wait_timeout' to unsigned.
It makes sense that the timeout value is unsigned, it also
resolves build errors on some platforms.
2020-12-04 11:44:50 +01:00
mean
e3fd12ebc6 gd32f1/f3 detection and ram/flash autoset 2020-12-03 11:16:47 +01:00
Jonathan Giles
575c25e570 Add support for STM32F1 clone with new AP_DESIGNER id 2020-12-01 10:23:16 +01:00
Uwe Bonnes
48a79ff9da adiv5: More checks for a sensible DPIDR. 2020-11-29 21:11:11 +01:00
Uwe Bonnes
752bc26536 adiv5: Fix memleak with duplicated base. 2020-11-29 21:11:11 +01:00
Uwe Bonnes
acec489647 adiv5_jtagdp: Always set idcode. 2020-11-29 21:11:11 +01:00
Uwe Bonnes
f45c56af83 adiv5/swdp: Check early for valid DP idcode. 2020-11-29 15:48:50 +01:00
Uwe Bonnes
7df314e265 Firmware/Jlink: Fix double free when debug power-up fails (#780) 2020-11-29 15:48:50 +01:00
Uwe Bonnes
bf548e92c0 swd: After write low_access, always append 8 clk to move data through SW-DP.
Especially needed when leaving the debugger or during debug unit power-up.

ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
tells to clock the data through SW-DP to either :
- immediate start a new transaction
- continue to drive idle cycles
- or clock at least 8 idle cycles

Implement last option to favour correctness over slight speed decrease

Implement only for adapters where we assemble the seq_out_parity in our code,
as on firmware, ftdi and jlink. Hopefully the high level adapters do it right.

Reverts 2c33cde63fe779d3019fe8f63dd4420cb960bbfe and
cde7726b8730242cd40a9974d129b46af80c68af
2020-11-27 22:26:48 +01:00
Uwe Bonnes
3ee31473c6 cortexm.c: LPC15xx has designer 43b and Partno 4c3
Thanks to JojoS!
2020-11-27 22:26:48 +01:00
Uwe Bonnes
19e1fddba2 adiv5: Remove unnescessary read. 2020-11-27 22:26:48 +01:00
Uwe Bonnes
cda83d3084 Fix memleaks.
Happened e.g. when Stlink could not enter debug or when cortexm_prepare timed out.
2020-11-27 22:26:48 +01:00
Uwe Bonnes
9ac5adfcef adiv5: Additional decoding. 2020-11-27 22:26:48 +01:00
Uwe Bonnes
d78d7838d3 stm32f1: Always read DBGMCU_IDCODE for t->idcode (#770)
At least STM32F042 has 0x440 as romtable partno vs 0x445 as DBGMCU_IDCODE.
Thanks to Andrey Melnikov(aam335) for pointing out!
2020-11-27 22:26:48 +01:00
Uwe Bonnes
653d486ee2 cortexm: Store CPUID in target structure. 2020-11-27 22:26:48 +01:00
Uwe Bonnes
80154c5c7a adiv5_swdp: Fix more memory leak. 2020-11-27 22:26:48 +01:00
Noah Pendleton
35bcb4f7c6 Switch on the lpc546xx target
Enable the lpc546xx target. Tested on the LPCXpresso54628 dev board,
able to flash and debug.
2020-11-24 21:32:39 +01:00
Sean Cross
e9c02296f2 target: kinetis: add S32K118
This adds support for the NXP S32K118. This is an automotive-grade part
that is derived from the Kinetis line, so it has a very similar
interface to other parts in the family.

Signed-off-by: Sean Cross <sean@xobs.io>
2020-11-14 13:06:23 +01:00
jbuonagurio
f18be6ef7a Add support for Kinetis K12 and placeholders for other K-series MCUs 2020-11-07 12:44:05 +01:00
Uwe Bonnes
2c33cde63f cortexm.c/cortexm_halt_resume: Add some clock cycles to always get CPU going (#768) 2020-11-01 21:53:23 +01:00
Uwe Bonnes
1f7a716710 adiv5.c: Run cortexm_prepare on all suspected CortexM instances.
Gets all debug units of the second CPU of a STM32H745 visible.
2020-10-23 09:40:15 +02:00
Uwe Bonnes
18673d9a56 adiv5: Rework DP/AP refcounting.
ASAN non longer reports leaks with the STM32H745.
2020-10-23 09:40:15 +02:00
Uwe Bonnes
f76a7c4e92 adiv5: Release devices after scan.
Before, scanning only kept device stopped until POR or attach/detach cycle.
2020-10-23 09:40:15 +02:00
Uwe Bonnes
59dc1b7eb4 cortex-m7: Give hint about buggy core revision. 2020-10-23 09:40:15 +02:00
Uwe Bonnes
976c763747 jtag remote: Start fixing handling M0 (second jtag) for LPC4322 in high-level
- LPC11: Only print none-null unknown idcodes.
2020-10-23 09:40:15 +02:00
Uwe Bonnes
c161521c26 cortexm: Designer ARM must be in the default path when probing. 2020-10-23 09:40:15 +02:00
Uwe Bonnes
cdd07544d5 Cortexm: Allow pure debug on devices not yet handled for flashing
- Recognize STM32L552 and MIMXRT10XX
- Fix another PIDR
- Fix bad debug print string.
2020-10-23 09:40:15 +02:00
Uwe Bonnes
0ffb4f7b18 cortexm: Fix protected SAM detection
- Only run cortex_prepare() if reading cidr fails
- With Atmel DSU detected, run cortexm_probe()
2020-10-17 12:49:37 +02:00
Uwe Bonnes
5bc743d221 samd: Propagate security after setting security by chip reset. 2020-10-17 12:49:37 +02:00
Uwe Bonnes
8b929c12c9 hosted/jtag: Transfer jtag_devs to firmware. 2020-10-16 20:03:03 +02:00
Uwe Bonnes
3d92b82678 jtag: Use index and not device structure for jtag_dev_write_ir and jtag_dev_shift_dr 2020-10-16 20:03:03 +02:00
Uwe Bonnes
7ccf0d3e03 jtag_dev_t: Make dev, idcode and desc less generic.
No codechange intended.
2020-10-16 20:03:03 +02:00
Uwe Bonnes
87b546777a nrf51: Be more verbose about the protection status. 2020-10-16 12:16:33 +02:00
Richard Meadows
4108b649c2 stm32h7: Add support for new product lines
Add support for:
* STM32H7B3/B0/A3 (RM0455)
* STM32H723/33/25/35/30 (RM0468)

Successfully tested with:
* STM32H7A3ZIT (RM0455)
* STM32H747XIH (check for regressions)
2020-10-10 22:09:34 +02:00