Problem: On some boards flashing hanged.
Cause: Releasing SRST caused a slow rise of nRST and flashing
started while the target still was in reset.
Attention: platform_delay(ms) only resolved 0.1 s.
Nucleo-P boards have SRST unconnected to target nRST by default.
With 128 bytes for both usb_uart buffers, traceswo gives errors!
Keep the size for the receive buffer and diminisch the transmit buffer,
as there is no flow control to the device.
Probably related to https://github.com/libopencm3/libopencm3/issues/477
or bootloader is write protected.
Device read protection or write protection on first 4 bootloader pages
can only be removed by mass erase. Triggering mass erase with a program
running from flash is doomed for failure.
User can force bootloader update, at their own risk to brick the device.
Complements #204.
STLinkV2-1 has F103CB on board! F103C8 on older Stlinks can use upper flash
with hopefully acceptable error rate.
For F103C8 devices, user has to give the force option to dfu-utils.
As the first 4 pages of the bootloader will always keep write protection
once read protection is applied, with the second update of the bootloader
only the higher pages where updated effectivly.
In most cases this resulted in an inaccessible device!
This is a questionable fix for the Kinetis K22F that samples
this pin on release from reset to enable its EzPort which
makes the flash unusable and disables the rest of the micro.
Although the devices are only documented to have 64K flash,
they have been obeserved to have a full 128K, although the undocumented
half may be untested and have problems.
1) This version uses a direction control level shifters. We need to control
the direction of the TMS/SWDIO pin.
2.1) Because we want to support a large voltage range for SRST we use an
external dual MOSFET for asserting and sensing the SRST line. We have
added the hardware version 3 to be handled the same way as version 0.
Meaning using separate pins for assertion and sensing of the SRST line.
2.2) The new SRST sense circuit is inverting, thus we have dedicated
code for hardware version 3 that inverts the SRST status pin on read.
I was stuck trying to debug the issue why my probe would not find any attached targets. This is because I was doing the pin mapping as per the comments, and not the actual code. There is a mismatch!
This PR updates the comment to reflect the values set in code. :)
This adds a new function to the internal target interface
to allow the target to get control before reset is complete
so that it can do any additional work. On this target there
is a proprietary internal bit that has to be reset in some
cases to allow the core to continue operating.
