29 Commits

Author SHA1 Message Date
Alexandru Gagniuc
6f30e76c61 lm4f: Enable FPU using the vector_chipset hook
Newlib and arm-non-eabi-gcc likes to use the FPU by default on
Cortex-M4F chips. AS a result, do the right thing and enable the FPU
by default.

This fixes issues where code is generated which uses the FPU and
causes the CPU to hard-fault. This change removes the responsibility
of FPU initialization from the application code.

This makes the lm4f consistent with other M4+ devices that enable the
FPU in core library startup code.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>
2016-08-15 20:58:34 +00:00
Karl Palsson
f6c7d92c4f stm32l4: enable FPU in chipset specific startup.
Helpful if you don't like seeing:
(gdb) vecstate
HardFault: forced due to escalated or disabled configurable fault (see below)
UsageFault due to access to disabled/absent coprocessor
2016-03-30 16:59:57 +00:00
Kuldeep Singh Dhaka
77354cb371 Inital support for EFM32LG 2015-12-13 19:56:19 +01:00
Karl Palsson
507c184456 stm32l4: initial memorymap and vector support
Values from RM0351rev1, with the correction of the duplicate TIM1_CC entry.

Only stub support so far, but this opens up the beginning of build testing.
2015-11-10 23:47:57 +00:00
Frantisek Burian
3ef2c38120 [stm32f7] Add initial support of the family, GPIO support.
Most changes are noise from doxygen.
Readme udpated to explain newer FP_FLAGS for m7
stm32f7 library is skipped if the toolchain doesn't support it yet.
2015-10-15 10:34:28 +00:00
Frantisek Burian
f9152eb00a [stm32l0] Initial support for STM32L0 architecture, Add GPIO peripheral 2014-10-15 19:31:41 +02:00
Stefan Agner
07b7d3e805 vf6xx: initial add of Vybrid VF6xx support
Freescale Vybrid is a familiy of ARM SoC, wheras the VF6xx models
have two cores in one SoC, a Cortex-A5 and a Cortex-M4. This adds
initial support for the Cortex-M4 in the libopencm3 library.

By using two different ram areas (pc_ram and ps_ram) the user can
put the code in a RAM area bounded to the code bus. The data can
be stored in the data area. However, currently the initial values
of for the variables in the data section are stored in the code
section and copied to the ram section by the initialization code
(like it's copied from ROM to RAM on microcontrollers).
2014-10-15 19:31:01 +02:00
Felix Held
641fbffe9a [sam3a] add irq table and memory map 2014-02-24 02:32:38 +01:00
Felix Held
b5d937a00c add memory map and irq table for sam3s and sam3u devices 2014-02-06 23:06:55 +01:00
Karl Palsson
822654b16b [stm32f3] Properly turn on the FPU
The vector chipset file was added, but not included in the dispatcher.
Fixes github issue #201
2013-09-23 14:32:35 +00:00
BuFran
18c4d299c1 [STM32F0] Add preliminary support for the family 2013-08-22 17:18:35 -07:00
Federico Ruiz Ugalde
0ca18eb09f Added interrupts for f3, Pre_main rutine in vector_chipset, nvic.h modified to include f3. 2013-07-07 16:01:46 -07:00
Ben Gamari
78081bd794 lpc43xx: Add irq.yaml for M0 core 2013-07-07 13:52:16 -07:00
Ben Gamari
c25461dfce lpc43xx: Move M4 specific files to m4/ 2013-07-07 13:52:15 -07:00
Piotr Esden-Tempski
7df63fcae0 First coarse run to fix coding style in locm3.
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.

We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
  only contain one statement. Otherwise it is easy to introduce an
  error.

Checkpatch needs to be adapted to reflect those changes.
2013-06-12 18:22:56 -07:00
Gareth McMullin
ce3e3dc39b Split sam3x/sam3n support. 2013-06-02 18:01:38 -07:00
Gareth McMullin
f0bace7838 sam3x support. 2013-05-10 14:01:16 -07:00
Alexandru Gagniuc
60ceec0266 lm4f: Compile in the interrupt vector table
Add an "#ifdef(LM4F)" clause to include/libopencm3/dispatch/nvic.h
and lib/dispatch/vector_nvic.c. This compiles in the vector table
and allows interrupts to be used.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-12-31 01:35:27 -06:00
Karl Palsson
ce8f47e7df Enable nvic and exti support for L1
And include an example that uses it.
2012-11-07 21:54:18 +00:00
chrysn
a1f4c29872 Merge branch 'efm32'
this adds support for energy micro's efm32 tiny gecko, gecko, leopard gecko and
giant gecko series.

also, the experimental libopencmsis is included in this branch, as it is
required for full operation of the free energymicro standard library
2012-10-29 14:44:37 +01:00
Silvio Gissi
0a1cf977eb Added irq.yaml to lpc_13xx and lpc_17xx families 2012-10-21 08:54:40 +02:00
chrysn
a433217c5d Merge branch 'generalizations' into efm32 2012-10-19 19:29:32 +02:00
chrysn
14a5fc78cf completing dispatch
the LM3S irq list was previously unused as it was missing in the
dispatch files; now it got added. (before HEAD^, it wouldn't have made
any difference because the discriminating constant wasn't defined
anyway)

also, this enhances the warning messages
2012-10-19 19:10:42 +02:00
chrysn
ab5a544d45 added irqs for the rest of the efm32 devices 2012-10-19 01:11:43 +02:00
chrysn
d526dd3268 rename tinygecko->efm32tg everywhere 2012-10-19 00:59:49 +02:00
chrysn
d13043d787 change discriminator in efm32 series from TINYGECKO to EFM32TG 2012-10-19 00:31:10 +02:00
chrysn
0548317683 fix bug resulting from equally named files
the local vector.o files shadowed the ../cm3/vector.c from VPATH,
resulting in empty reset vectors.
2012-10-18 18:54:52 +02:00
chrysn
c69916ffb6 integrate irq2nvic_h script in buildprocess 2012-10-18 17:58:12 +02:00
chrysn
5afa53f01a drop two-line vector.c dispatchers in favor of central dispatch 2012-10-18 16:29:58 +02:00