The f107 ethernet peripheral is the same as in f4, and was pulled out
into lib/ethernet/mac_stm32fxx7.c in 52758bb8fdf065d46ef1ea21cc383e2dc74ee19b
This drops the duplicate code.
Fixes Github issue #694
The TSVREFE bit is defined to only be present on ADC1, so drop the
pointless adc argument. This has the added benefit of making the
API consistent with all other STM32 adc parts.
Use same names as adv-v2 peripheral uses. F1 is the only v1 peripheral
adc that has calibration modes at all.
Old:
adc_calibration(ADC1); // blocking call
New (blocking):
adc_calibrate(ADC1);
New (asynch):
adc_calibrate_async(ADC1);
// do stuff
adc_is_calibrating(ADC1); // false when calibration finished
Old routines are preserved but marked deprecated for now.
At least temp sensor, vrefint and vbat/vlcd should have consistent names and
consistent doxygen.
Dropped channel definitions that are the same as the raw number.
As done by esden for the F4, remove typedefs and add prefixes to clock enums
This extends this to all stm32 families.
Let's not hide the fact that these variables are structs/enums.
We are filling up the namespace badly enough, we should be prefixing as
much as we can with the module names at least. As users we already run
often enough in namespace colisions we don't have to make it worse.
* CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
* clock enums (PLL, HSI, HSE ...) prefixed with RCC_
* scale enum of pwr module prefixed with PWR_
Was only in the (obviously out of date) documented example and as a
declaration. No implementations. Dropping immediately, but documentation
still needs further work.
All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.
Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.
Fixes github issue #321
The breaking changes here changes in header location, and changes in driver
name passed down to the usb stack.
Changes affect: stm32f102/f103, stm32l1, and some f3 parts
* instead of the confusingly generic "usb" use the name "st_usbfs" for the USB
Full speed peripheral ST provides in a variety of their stm32 products.
Include directives should change as:
#include <libopencm3/stm32/usb.h> => <libopencm3/stm32/st_usbfs.h>
* instead of the confusingly specific "f103" name for the driver, use
"st_usbfs_v1" [BREAKING_CHANGE]
Instead of:
usbd_init(&stm32f103_usb_driver, .....) ==>
usbd_init(&st_usbfs_v1_usb_driver, .....) ==>
The purpose of these changes is to reduce some confusion around naming, but
primarily to prepare for the "v2" peripheral available on stm32f0/l0 and some
f3 devices.
Work by Frantisek Burian, Kuldeep Singh Dhaka, Robin Kreis, fenugrec and zyp
on irc, and all those forgotten.
This adds MCO source selection to some targets, and removes and standardizes
the mask/shift usage for all targets. For devices that support MCO2, this
supports only MCO1. No attempt has been made to extract MCO prescaler, which
is not available on all F1 and F3.
Rename rcc_ppre1_frequency and rcc_ppre2_frequency to rcc_apb1_frequency and rcc_apb2_frequency
Also add rcc_ahb_frequency (although it is not set correctly in all cases) which will be fixed by
the rcc commits later. Also fixup the only use in the library of these variables, the USART code.
And fix the typos that resulted
Make l1 generic too
F100 has more remap options than F10x, particularly on the High Density
devices.
Fixes github issue #365
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
The bits definitions for direct manipulation were missing, and should be
present for completeness. However, this only affects the legacy (error prone)
API, replaced some time ago.
old and error prone: (stop using code like this)
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM16EN);
rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM16RST);
new:
rcc_periph_clock_enable(RCC_TIM16);
rcc_periph_reset_{pulse,hold,release}(RCC_TIM16);
Fixes github issue #361
Latest versions of all reference manuals refer to the address as SPIx_BASE, and
simply name some of the individual registers as SPI_I2SXXXX. Likewise, the
interrupts are simply SPIx, not SPIx/I2Sx. Rather than hacking more duplicates
into the F0 and L0 parts where this was turning up, remove the pointless _I2S_
from SPI2/SPI3 and make it all consistent
Compile tested only, with the examples collection.
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Fixes#331Fixes#347
to remove variations, redundancies, add missing, fix errors. All c files
refer only to the dispatch style headers in /include/stm32. Those headers
#include memorymap.h and cm3/common.h. All references to
these are removed from the family specific headers. Ethernet untouched as
it appears incomplete.
Added dummy spi.c for F0/F3. Fix some doxygen anomalies.
When compiling with all warnings enabled, some defines can lead to
warning due to missing unsigned type suffix:
warning: integer overflow in expression [-Woverflow]
This fix should not affected behavior at all, since calculation with
such overflows lead to the same actual address when writing to that
location. However, it makes the warning disappear and also defines
the right data type for a memory location.
Extension of code for STM32F1 to allow for dual bank series XL.
Small changes to documentation for F2, F4 and L1 to add a parameter reference.
Tested with STM32F103RBT6
(note: tests show that the PG bit must be cleared after programming, otherwise
a subsequent erase attempt fails. This has been added to flash_program_half_word
for F0 and F1 only. A fix for the other families is not included in this PR.)
This unifies stm32f1, l1, and f4 convenience functions for adc. The code
should be useable for f2 and f37x as well, but that needs hardware for testing,
and there was no existing implementation. This is the reason for the
"adc_common_v1.c" name, as trying to put all the different families into the
common file name has become too cumbersome.
All of the deprecated routines have been dropped, they've been marked
deprecated for a very long time now, and porting them seemed unnecessary.
This has been tested on f1, l1 and f4 discovery boards, and is based on some
existing l1/f1 unification code from
https://github.com/karlp/libopencm3/tree/rme_l1_master
This pulls out all the common header definitions for the F1, L1, F4 and F37x
parts. It's verified against the datasheet for F2 as well, but we don't have
any good F2 test boards or any support for that yet. (The F2 header would be
_exactly_ the same as the F4 header, so it's a target for a future round of
unification, not this one)
Tested with f1, f4 and l1 examples from the examples repository.
So that the navigation pane works correctly in browsers.
Some additional doc fixes put in where found (but many more still to go).
Added some dummy .c and .h files to bring the associated docs into line.
makefile changed to allow 'make html' as well as 'make doc' (the latter only does html anyway).
This converts all the YAML files to JSON files, as json parsing is built
into python instead of being a separate library requiring installation.
YAML is a superset of JSON, but putting comments in is not quite as obvious
as it is in yaml.
The following glue was used to convert yaml to json:
python -c 'import sys, yaml, json; json.dump(yaml.load(sys.stdin), sys.stdout, indent=4)' < $1 > $2
Clearly I haven't tested this on every single platform, and this
doesn't address the large blobs of yaml in the lpc4300 scripts directory,
only the cortex NVIC generation process.
I've tested a few IRQ driven example apps, and I've checked the generated
output of some known cases like the LM3s that has explicit gaps, and they are
all generated correctly.
According to RM0090, page 301, paragraph 11.13.12 Note. (For F4, for F1 and F3 is it in the corresponding manuals)
The JSQR are filled always ending at SQR4 ie for those lists we must set this list:
(A) -> JSQ4 = A,
(A,B) -> JSQ3 = A, JSQ4 = B,
(A,B,C) -> JSQ2 = A, JSQ3 = B, JSQ4 = C,
(A,B,C,D) -> JSQ1 = A, JSQ2 = B, JSQ3 = C, JSQ4 = D,
The readed values are in correct order, starting from JDR1:
(A) -> JDR1 = A,
(A,B) -> JDR1 = A, JDR2 = B,
(A,B,C) -> JDR1 = A, JDR2 = B, JDR3 = C,
(A,B,C,D) -> JDR1 = A, JDR2 = B, JDR3 = C, JDR4 = D,
DFF exists at bit 11 for f1, f2, f4 and l1, but the f0 and f3 have that bit as
CRC len and use CR2 for data size bits instead. The merging of the F3 and F0
and attempts to put common data in common places broke the l1 code.
F3 and F0 SPI headers are still almost completely identical.
STM32L1 has a different set of offsets, not just a different base
address, so we can't have common registers definitions. Also, out of
F0,F1,F2,F3,F4,L1, only the F1 has the odd note about 2x16bit registers
and 2x32bit registers with one 16bit register marked as "This field
value is also reserved for a future feature." Therefore, replace the
awkward reading out as multiple words and just copy them in.
F0,F2,F3,F4 were missing definitions altogether.
This does _not_ attempt to address the problem of the mismatched base
addresses for Medium+ and High Density L1 parts.
We don't support f0 yet so let's not fool anyone. We may rename those
files back again if when we cross check that it is actually true this
file supports f0.
In places where we were defining memory mapped peripheral buffers we
were using directly a cast to "volatile int_type *". For consistency we
should use dereferenced accessor like: &MMIO32(address)
