2 Commits

Author	SHA1	Message	Date
Guillaume Revaillot	ebd265ce42	stm32g0: rng: typo in header.	2019-12-25 20:34:11 +00:00
Guillaume Revaillot	38006c3c82	stm32g0: add rng. ... Regular rng peripheral, with one additional bit : clock error detection apparently available on l4 chips). Curiously, Clock error detection is _disabled_ when bit is set, but bit is cleared by default, so peripheral / clock error detection behaves like all other chips.. NB: RNG need proper rcc_ccicr_rngsel bits set to work, no clock is set by default. Note also that on that chip fRNGCLK must be higher than fHCLK/32	2019-06-13 12:04:58 +02:00