2 Commits

Author	SHA1	Message	Date
Guillaume Revaillot	f99e711873	stm32g0: lptim: add additional cr bits and cfgr2 reg.	2019-07-05 11:43:11 +02:00
Guillaume Revaillot	811aebf096	stm32: lptimer: enable lptimer.h usage on f4,f7,l4 and g0 chips.	2019-07-05 10:48:55 +02:00