45 Commits

Author SHA1 Message Date
Koen De Vleeschauwer
54ee00b0f6 set semihosting sys_clock time origin 2020-05-13 17:50:39 +02:00
Sid Price
923949d5dd Fixed variable/function name clash building on Windows 2020-05-03 15:45:31 +02:00
Koen De Vleeschauwer
9f8c7be360 semihosting 2020-05-02 12:55:29 +02:00
Koen De Vleeschauwer
8851504a41 new semihosting commands 2020-04-23 09:43:46 +02:00
Uwe Bonnes
a0e42e229b Make more things static.
No functional change intendend.
2020-03-26 18:44:19 +01:00
Uwe Bonnes
effd43ce38 Harden cortexm_reset() and remove double reset(#601)
Thanks to Dave Marples <dave@marples.net> for input.
- Issue only one reset. Start with SRST. Only if not seen, use SYSRESETREQ
- Wait for release of DHCSR_S_RESET_ST before issuing more commands
- Add timeout to catch reset line stuck low
- Remove AP errors
2020-03-25 11:22:14 +01:00
Ken Healy
26216beaab Microchip SAM D51 / E5x support
Adds a target driver for Microchip SAM D51 / E5x family.

Tested on SAMD51G19A and SAMD51J19A. According to the datasheet, the
D51 / E5x family share the same core feature set, differing only in the
addition of CAN (E51) or ethernet controllers (E53/54). All members of
the family should be equivalent from a debug and programming perspective.
2019-11-17 12:45:49 +01:00
Gareth McMullin
e6504e149b cortexm: Implement single register read/write 2019-09-01 20:38:38 +02:00
Uwe Bonnes
d39dc34382 pc-stlinkv2: Fix reg_read|write
- Fix wrong placed brace in cortexm_regs_write()
- Start writing with r0
- With register read, save only registers listed
2019-09-01 12:11:37 +02:00
Uwe Bonnes
6bf4fd3598 pc-stlinkv2: CPU register read and write must be done with the AP set.
FIXME: Writing CPU registers on M4 of STM32H745 seems not to work.
2019-08-27 15:13:15 +02:00
Uwe Bonnes
dd3cb193f3 Indicate the Core in the Target list. 2019-07-17 17:38:21 +02:00
Uwe Bonnes
9ed26645d3 Add pc_stlinkv2 platform, running on host, talking to original StlinkV2/3.
Stlink firmware needs to be recent.
2019-07-17 17:38:01 +02:00
Richard Meadows
600bc9f029 Generate DEBUG warnings and return if malloc/calloc fail.
This is will make debugging earier if this does happen, rather than
dereferencing the null pointer (or passing it to memcpy, or worse).

blackmagic PR #475
2019-05-26 18:56:12 +02:00
Jeremy Elson
3235fa2005 Improve parsing of commands that require enable or disable arguments:
* Accept prefixes of the words 'enable' and 'disable'
* Prevent silent failures on parse errors
* Print status after flag changes
* Fix missing includes
2019-03-19 12:56:44 -07:00
newbrain
8de1b45c85 Kinetis KE04: Flash and debug support
Support for Kinetis KE04 8KiB, 64KiB and 128KiB variants in nxpke04.c
Target monitor commands for sector and mass erase.
Changes to kinetis.c MDM-AP target to support KE04.
Only KE04Z8 tested in HW.
2019-02-17 22:48:23 +01:00
Josh Robson Chase
02b9d5f1ac Add delay to cortexm_reset 2019-01-07 13:32:17 +13:00
Uwe Bonnes
8d6092b73f cortexm_forced_halt: Only release SRST after "Halt on reset" command.
This should make life easier if program remaps JTAG/SWD pins so that
with program running, JTAG/SWD access is impossible.
2019-01-07 13:22:01 +13:00
Uwe Bonnes
3ebf049424 cortexm: Only force halt before probe if idcode is unknown and ROM TABLE unreadable. 2019-01-07 13:22:01 +13:00
Uwe Bonnes
525b90d4e5 cortexm: Only force halt before probe() if probe was forced. 2019-01-07 13:22:01 +13:00
Uwe Bonnes
cde7726b87 cortexm: detach still needs extra cycles. 2019-01-07 13:22:01 +13:00
Uwe Bonnes
f5cf6d4497 adiv5_swdp: Add extra idle cycles with write transactions.
These extra cycles are needed by some CPU, e.g. STM32L0x1 to cross the SWCLK
/HCLK domains. Revert insufficient #373 also tackling that problem.

Thanks to Thorsten von Eicken for pointing out.
2018-09-06 17:29:20 +02:00
Rik van der Heijden
f39701c4c8 Move the LPC17xx probe function down since it performs an IAP call which can hang when performed on other devices than a LPC17xx 2018-09-05 17:40:02 +02:00
Uwe Bonnes
f234074099 stm32h7: Start of support.
Implement probe, memory map, erase, write, uid, crc, parallelism.
2018-07-27 10:59:54 +02:00
Uwe Bonnes
139707c5c0 cortexm/detach: Add a dummy transaction after cleaning DHCSR.
This replaces the seemingly superflous swdptap_seq_out() at
the end of adiv5_swdp_low_access() needed to continue after detach.
2018-07-19 10:57:41 +02:00
Gareth McMullin
b2defad844
Merge pull request #356 from UweBonnes/probe_halted
Probe halted
2018-06-21 10:06:56 -07:00
Uwe Bonnes
54f73858f9 Provide a target function to write with given size. 2018-06-16 13:30:08 +02:00
Uwe Bonnes
17b817f37b cortexm: Allow to set timeout to wait for halt.
This allows to gain access to devices spending long time in WFI without
the need for a reset, at the expense of possible long waiting times.
Using Reset means loosing the device runtime context.
2018-06-13 14:03:50 +02:00
Uwe Bonnes
9e365a58f7 Cortex-M: Try harder to halt devices in WFI.
E.g. STM32F7 and L0 need multiple C_DEBUG and C_HALT commands to halt
the device.
2018-06-13 14:02:43 +02:00
newbrain
ae6f0eadc9 Support for MSP432 TI MCUs (#353)
Introduces flashing and debugging support for Texas Instruments MSP432
series of MCUs
2018-06-07 08:34:21 +12:00
Gareth McMullin
cfaa5ea963 Merge branch 'korken89-master' 2018-03-27 13:01:06 +13:00
Gareth McMullin
76bfb4929d Use lowercase register names. 2018-03-27 13:00:39 +13:00
Akila Ravihansa Perera
471ce2547c Added LPC17xx support (#317) 2018-03-25 12:53:30 -07:00
Emil Fresk
1ee6d4503e Update to split 'special' into its sane parts (update from @mubes) 2018-03-24 16:44:59 +01:00
Gareth McMullin
c53a12bfd1 cortexm: Better cache support for Cortex-M7
- On probe, read CTR for cache presence and minimum line length
- Make D-Cache clean a function
- Clean before memory reads
- Clean and invalidate before memory writes
- Flush all I-Cache before resume
2017-10-12 09:26:01 +13:00
Nick Downing
0e5b3ab00e Make Cortex M driver write DCCIMVAC (Data cache clean and invalidate by address to the PoC=Point of Coherency) prior to reading or writing each 32 bytes of RAM 2017-10-12 08:41:58 +13:00
Stefan Agner
3c06396c8e Constify strings and constant structs 2017-04-22 13:50:04 -07:00
Gareth McMullin
e4de689a09 cortexm: Check halt reason on stub exit. 2017-04-12 11:37:42 +12:00
Chuck McManis
085c980215 Remove EXTENDED_RESET define 2016-12-04 13:51:27 -08:00
Chuck McManis
a3c2592e44 Review feedback 2016-12-04 13:15:45 -08:00
Chuck McManis
0aef6c6774 SAM4L: Add extended reset to target interface
This adds a new function to the internal target interface
to allow the target to get control before reset is complete
so that it can do any additional work. On this target there
is a proprietary internal bit that has to be reset in some
cases to allow the core to continue operating.
2016-12-02 00:08:21 -08:00
Gareth McMullin
9a8cef04e0 Clean up debug format strings. 2016-09-29 21:31:18 -07:00
Gareth McMullin
9aacc18f60 target: Restructure internal break/watch handling.
cortexa: Implement soft breakpoints.
2016-07-13 08:31:09 +12:00
Gareth McMullin
9136cf4c98 target: target_halt_wait and target_check_hw_wp replaced with target_halt_poll.
The new function returns a stop reason which must be translated in gdb server.
In the case of a watchpoint hit, the address is returned by a pointer parameter.
Simplify the extenal interface for set/clear breaki-/watchpoints.
2016-07-13 08:31:09 +12:00
Gareth McMullin
aeaca988c3 target: Use new target_addr type consistently in external interface.
Flash routines still use uint32_t internally.
2016-07-13 08:31:09 +12:00
Gareth McMullin
b494279fe5 Move target files into separate directory. 2016-07-13 08:31:09 +12:00