Originally sourced from: https://github.com/libopencm3/libopencm3/pull/382
fixed some typos from the manual and poor merging/rebaseing,
and one judgment call on using a specific name for a conflicting
bit definition.
The stm32fx07 is common DesignWare IP, used in both STM32 and EFM32 chips.
Rename the files to make this more clear, and easier to use in other
targets.
Makefile doesn't even refer to it, and it's empty anyway. Not required
for doxygen purposes, (anymore?) so just drop it. File had _never_ been
included in the f3 makefile.
The ADC v2 peripheral doesn't have the same behaviour of starting, where
the hardware clears the bit immediately, on v2, it is not cleared until
the ADC is stopped, or the end of sequence flag is set.
Fixes https://github.com/libopencm3/libopencm3/issues/557
The SPI br parameter has always been the 3 bit fpclk divider field, and
was never a target or explicit bit rate. Correct the comments, and drop
the duplicate commentary that wasn't included in the doxygen output
anyway.
Fixes: a7a3770d Add initial SPI code
Use the usart-common base plus the usart-v2 code, instead of private
implementations. Less code, more common apis across targets.
Of note is the trick to make F0 look like it has an APB2 bus. It's the
only stm32 that doesn't have a documented APB2 bus, but still has
peripherals enabled via an "APB2" register, and they match how other
targets have an APB2. Simply make APB2 an alias of APB1, as it's only
used for clock speed detection.
This function was using apb1 for quite a few families instead of apb2.
This only mattered for L1 and F3, and for USART1/USART6, and only if
apb1 speed != apb2 speed.
Instead of using families explicitly, just check for the peripherals
themselves. On F0,F1,F2,F3,F4,F7,H7,L0,L1,L4, usart1/6 are _always_ in
the rcc_apb2 register and the other uarts are all on apb1.
(F0 doesn't actually _have_ apb2, but it's still called the apb2
register)
The ADVANCED_TIMERS define/check was added in 523943a as part of adding L1
support. The runtime checks against TIM1/TIM8 already existed. Since L1
doesn't have TIM1/TIM8, those names are undefined, resulting in a compilation
error until ifdeffed out.
Since I throw out all TIM1/TIM8 checks, there's no references to those names
left, thus no need to keep the ifdef either.
As for the registers themselves, l1/timer.h pulls in common/timer_common_all.h
which defines macros for the superset of all timers, so e.g. TIM_BDTR() is
still available regardless of whether or not the particular chip we're building
for has any timers with a BDTR register.
Very new gcc versions add a warning on switch cases that fall through.
While there's an option that accepts any comment as explaining it, it's
easier in our case to just use one of the "blessed" comments. We can't
use the [[]] attributes for standards code, and the gcc specific
attributes are worse than the comments. This has no functional change
whatsoever.
Clearly staging branch testers weren't testing.
Also, clearly the separation of RST_ bits and RCC_ bits is a complicated
annoyance.
Fixes: d9615a2eb728 update to modern include apis
Added the CAN1 compatibility aliases as has been done for adc and dac to
make code reuse easier. Only for the magic enums, the raw bit
definitions remain as per the ref mans
Originally suggested as https://github.com/libopencm3/libopencm3/pull/802
rcc_osc_bypass_enable and rcc_osc_bypass_disable have been copy/pasted
around for the last time! There's a compile bit to check for L0/L1, but
otherwise this is just code duplication for no gain.
