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25 Commits

Author SHA1 Message Date
Mike
34d0f64529 Nordic nRF51 series support 2014-05-01 15:09:59 +01:00
Gareth McMullin
3077472620 Unwind hardfaults in dual-stack mode. 2014-03-31 20:58:06 +13:00
Benno Leslie
3cce6f472c Add support for the SYS_WRITEC semihosting operation. 
This is implemented in the same manner as QEMU semihosting
support, specifically, a SYS_WRITEC results in a single
character write to STDERR.
 2013-10-05 13:14:03 +08:00
Gareth McMullin
d8f737fc53 Disable ADIv5 timeout while target is running. 2013-06-19 21:05:53 +12:00
Gareth McMullin
2d63dd4b5b Fix register array sizes. 2013-06-17 15:52:15 +12:00
Paul Fertser
df32aad757 semihosting: improve handling of console I/O 
This implements special handling for SYS_OPEN to catch requests for
":tt" which is reserved by ARM for console input/output. They're
mapped to the appropriate GDB file descriptors automatically.

An additional file handle offset is introduced because ARM doesn't
consider zero handle to be valid.

Signed-off-by: Paul Fertser <fercerpav@gmail.com>
 2013-05-18 15:33:58 +12:00
Gareth McMullin
5020d1f05d Move semihosting support to cortexm.c. 
Try to implement more syscalls.
 2013-05-18 15:33:58 +12:00
Paul Fertser
e0fc21a2a7 adiv5_swdp: allow to connect to a sleeping target by pulling SRST 
This patch introduces a new command, "connect_srst [enable|disable]"
which allows to enable special mode in which SRST would be pulled low
before the SWD scan till attaching to a target.

Since on Cortex-Mx the SRST signal doesn't gate JTAG and SWD, it's
possible to connect to a target while holding reset, ask it to stop at
reset vector and only then deassert reset, thus allowing to attach to
the kind of firmware that goes immediately to sleep or disables
debugging by other means early on start.

Tested on an STM32VLDiscovery board with STM32F100 configured to go to
STOP mode and executing WFI in the very beginning of main().

Signed-off-by: Paul Fertser <fercerpav@gmail.com>
 2013-05-14 12:32:44 +12:00
Gareth McMullin
2a46994b42 Fixed magic numbers for CSW access. 2013-01-11 10:02:34 -08:00
Gareth McMullin
2637f072a1 Probe function return bool, true if device identified. 
Correctly identify LM3S3748.
 2012-11-03 23:53:25 +13:00
Gareth McMullin
e1c1162a1a Recognise LPC43xx dual core devices. 2012-11-03 21:33:28 +13:00
Gareth McMullin
0990c2224c Allow target attachment to timeout and report failure. 
This is needed for if the target device is held in reset.
 2012-11-03 16:42:46 +13:00
Vegard Storheil Eriksen
faa43fdc92 Added support for STM32L1. 2012-10-25 21:44:26 +02:00
Gareth McMullin
9137c2d058 Add a copy of DEMCR to Cortex-M private data to preserve over 'run'. 2012-08-10 21:07:06 +12:00
Gareth McMullin
234d54c5a5 Correct stepping over programmed breakpoints. 
Fixes issue #2.
 2012-07-05 22:08:01 +12:00
Gareth McMullin
0433d3d12a cortexm: Moved all static data to the heap. 2012-07-05 21:26:26 +12:00
Gareth McMullin
0c379744e9 cortexm: Poll for S_RESET_ST in DHCSR to detect release from reset. 2012-07-05 20:12:18 +12:00
Gareth McMullin
5dff263078 Add delay after reset request. 
Hopefully this fixes problems observed with failing vFlashWrite.
 2012-07-01 22:40:43 +12:00
Gareth McMullin
d64cec686a Signal on halt is now returned by target_halt_wait(). 
Fault unwinding is now handled internally in target implementation.
GDB server doesn't need to know about it.
 2012-06-30 20:29:08 +12:00
Gareth McMullin
22993fb5bd Clear target error on attaching. 
Fixes possible lock-up on devices booting from blank flash.
 2012-06-28 20:11:53 +12:00
Gareth McMullin
0e768664ac Added 'vector_catch' command to control trapped vectors on Cortex-M. 2012-06-25 21:19:09 +12:00
Gareth McMullin
c09cbe8719 First cut at an Atmel SAM3X driver. 2012-06-22 23:13:25 +12:00
Gareth McMullin
33905d7203 Check target error after target specific probes. 2012-06-21 20:54:56 +12:00
Gareth McMullin
bc7e7d2112 Removed target header files containing a single prototype. 
Target probe prototypes are all in target.h now.
 2012-06-18 20:27:06 +12:00
Gareth McMullin
bc5a6f022b Renamed Cortex-M driver appropriately since it support M0, M3 and M4F. 2012-06-18 19:56:19 +12:00