10 Commits

Author SHA1 Message Date
Karl Palsson
c72f3d588a Surround all macro parameters with ()
All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.

Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.

Fixes github issue #321
2015-10-14 22:15:15 +00:00
Karl Palsson
b1e495f51a stm32f3: adc: Add support for sequence completion flags
The f3 adc has separate bits for end of conversion and end of sequence.
Support those fully, with the regular enable/disable irq methods, and
the flag checking methods.

Discovered in github bug: #493
2015-07-29 13:28:18 +00:00
Karl Palsson
e65140d0d3 stm32f3: adc: remove invalid eoc group methods.
This code was copied from the f4, and blindly modified to make it seem
to work.  The f3 has separate flags for EOC and EOS, it doesn't use a
second bit to configure what the EOC bit does.

Consequently, update the documentation to correctly indicate that the
EOC bits are only set per conversion.

Discovered in github bug: #493
2015-07-29 13:22:17 +00:00
Ken Sarkies
7816501dbc Changes to the header includes for all STM32 peripherals
to remove variations, redundancies, add missing, fix errors. All c files
refer only to the dispatch style headers in /include/stm32. Those headers
#include memorymap.h and cm3/common.h. All references to
these are removed from the family specific headers. Ethernet untouched as
it appears incomplete.

Added dummy spi.c for F0/F3. Fix some doxygen anomalies.
2014-03-11 16:40:31 +00:00
Karl Palsson
3eaeaf693c stm32: ADC peripheral style 1 header unification
This pulls out all the common header definitions for the F1, L1, F4 and F37x
parts.  It's verified against the datasheet for F2 as well, but we don't have
any good F2 test boards or any support for that yet.  (The F2 header would be
_exactly_ the same as the F4 header, so it's a target for a future round of
unification, not this one)

Tested with f1, f4 and l1 examples from the examples repository.
2014-02-05 10:38:45 +00:00
Piotr Esden-Tempski
a909b5ca9e [Style] Global style fix run. 2014-01-03 01:07:30 +01:00
BuFran
6570f6eb07 Fix the order of ADC injected channel list
According to RM0090, page 301, paragraph 11.13.12 Note. (For F4, for F1 and F3 is it in the corresponding manuals)

The JSQR are filled always ending at SQR4 ie for those lists we must set this list:

(A)       ->                               JSQ4 = A,
(A,B)     ->                     JSQ3 = A, JSQ4 = B,
(A,B,C)   ->           JSQ2 = A, JSQ3 = B, JSQ4 = C,
(A,B,C,D) -> JSQ1 = A, JSQ2 = B, JSQ3 = C, JSQ4 = D,

The readed values are in correct order, starting from JDR1:

(A)       -> JDR1 = A,
(A,B)     -> JDR1 = A, JDR2 = B,
(A,B,C)   -> JDR1 = A, JDR2 = B, JDR3 = C,
(A,B,C,D) -> JDR1 = A, JDR2 = B, JDR3 = C, JDR4 = D,
2013-12-04 22:03:23 +00:00
BuFran
d63bf5ac64 [STM32F3:doc] Add doxygen documentation page to output 2013-08-22 23:08:52 -07:00
Piotr Esden-Tempski
62e6635992 [Style] Fixed style in the newly added F3 code. 2013-07-07 16:01:52 -07:00
Federico Ruiz Ugalde
0a39eab19a Missing files for adc stm32f3 support added. 2013-07-07 16:01:47 -07:00