139 lines
5.7 KiB
C
139 lines
5.7 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_MEMORYMAP_H
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#define LPC43XX_MEMORYMAP_H
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#include <libopencm3/cm3/common.h>
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/* --- LPC43XX specific peripheral definitions ----------------------------- */
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/* Memory map for all busses */
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#define PERIPH_BASE_AHB 0x40000000
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#define PERIPH_BASE_APB0 0x40080000
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#define PERIPH_BASE_APB1 0x400A0000
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#define PERIPH_BASE_APB2 0x400C0000
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#define PERIPH_BASE_APB3 0x400E0000
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/* Register boundary addresses */
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/* AHB (0x4000 0000 - 0x4001 2000) */
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#define SCT_BASE (PERIPH_BASE_AHB + 0x00000)
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/* PERIPH_BASE_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */
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#define DMA_BASE (PERIPH_BASE_AHB + 0x02000)
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#define SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)
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#define SDIO_BASE (PERIPH_BASE_AHB + 0x04000)
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#define EMC_BASE (PERIPH_BASE_AHB + 0x05000)
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#define USB0_BASE (PERIPH_BASE_AHB + 0x06000)
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#define USB1_BASE (PERIPH_BASE_AHB + 0x07000)
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#define LCD_BASE (PERIPH_BASE_AHB + 0x08000)
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/* PERIPH_BASE_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */
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#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)
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/* 0x4001 2000 - 0x4003 FFFF Reserved */
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/* RTC domain peripherals */
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#define ATIMER_BASE 0x40040000
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#define BACKUP_REG_BASE 0x40041000
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#define PMC_BASE 0x40042000
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#define CREG_BASE 0x40043000
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#define EVENTROUTER_BASE 0x40044000
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#define OTP_BASE 0x40045000
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#define RTC_BASE 0x40046000
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/* 0x4004 7000 - 0x4004 FFFF Reserved */
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/* clocking/reset control peripherals */
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#define CGU_BASE 0x40050000
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#define CCU1_BASE 0x40051000
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#define CCU2_BASE 0x40052000
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#define RGU_BASE 0x40053000
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/* 0x4005 4000 - 0x4005 FFFF Reserved */
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/* 0x4006 0000 - 0x4007 FFFF Reserved */
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/* APB0 ( 0x4008 0000 - 0x4008 FFFF) */
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#define WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)
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#define USART0_BASE (PERIPH_BASE_APB0 + 0x01000)
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#define UART1_BASE (PERIPH_BASE_APB0 + 0x02000)
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#define SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)
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#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
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#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)
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#define SCU_BASE (PERIPH_BASE_APB0 + 0x06000)
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#define GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)
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#define GPIO_GROUP0_INTRRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)
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#define GPIO_GROUP1_INTRRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)
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/* 0x4008 A000 - 0x4008 FFFF Reserved */
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/* 0x4009 0000 - 0x4009 FFFF Reserved */
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/* APB1 (0x400A 0000 - 0x400A FFFF) */
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#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)
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#define I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)
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#define I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)
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#define I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)
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#define C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)
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/* 0x400A 5000 - 0x400A FFFF Reserved */
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/* 0x400B 0000 - 0x400B FFFF Reserved */
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/* APB2 (0x400C 0000 - 0x400C FFFF) */
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#define RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)
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#define USART2_BASE (PERIPH_BASE_APB2 + 0x01000)
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#define USART3_BASE (PERIPH_BASE_APB2 + 0x02000)
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#define TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)
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#define TIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)
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#define SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)
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#define QEI_BASE (PERIPH_BASE_APB2 + 0x06000)
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#define GIMA_BASE (PERIPH_BASE_APB2 + 0x07000)
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/* 0x400C 8000 - 0x400C FFFF Reserved */
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/* 0x400D 0000 - 0x400D FFFF Reserved */
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/* APB3 (0x400E 0000 - 0x400E FFFF) */
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#define I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)
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#define DAC_BASE (PERIPH_BASE_APB3 + 0x01000)
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#define C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)
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#define ADC0_BASE (PERIPH_BASE_APB3 + 0x03000)
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#define ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)
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/* 0x400E 5000 - 0x400E FFFF Reserved */
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/* 0x400F 0000 - 0x400F 0FFF Reserved */
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#define AES_BASE 0x400F1000
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/* 0x400F 2000 - 0x400F 3FFF Reserved */
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#define GPIO_PORT_BASE 0x400F4000
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/* 0x400F 8000 - 0x400F FFFF Reserved */
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#define SPI_PORT_BASE 0x40100000
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#define SGPIO_PORT_BASE 0x40101000
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/* 0x4010 2000 - 0x41FF FFFF Reserved */
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/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */
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/* 0x4400 0000 - 0x5FFF FFFF Reserved */
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/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */
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#endif
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