be841154a9
Most of the changes went to i2c_common_all.h file. F3 is considerably different than all the other in i2c.
757 lines
21 KiB
C
757 lines
21 KiB
C
/** @addtogroup i2c_defines
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@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H
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The order of header inclusion is important. i2c.h includes the device
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specific memorymap.h header before including this header file.*/
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/** @cond */
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#if defined(LIBOPENCM3_I2C_H) || defined(LIBOPENCM3_I2C_COMMON_F24_H)
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/** @endcond */
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#ifndef LIBOPENCM3_I2C_COMMON_ALL_H
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#define LIBOPENCM3_I2C_COMMON_ALL_H
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#include <libopencm3/cm3/common.h>
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/**@{*/
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/* --- Convenience macros -------------------------------------------------- */
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/* I2C register base addresses (for convenience) */
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/****************************************************************************/
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/** @defgroup i2c_reg_base I2C register base address
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@ingroup i2c_defines
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@{*/
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#define I2C1 I2C1_BASE
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#define I2C2 I2C2_BASE
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/**@}*/
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/* --- I2C registers ------------------------------------------------------- */
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/* Control register 1 (I2Cx_CR1) */
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#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00)
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#define I2C1_CR1 I2C_CR1(I2C1)
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#define I2C2_CR1 I2C_CR1(I2C2)
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/* Control register 2 (I2Cx_CR2) */
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#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04)
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#define I2C1_CR2 I2C_CR2(I2C1)
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#define I2C2_CR2 I2C_CR2(I2C2)
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/* Own address register 1 (I2Cx_OAR1) */
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#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08)
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#define I2C1_OAR1 I2C_OAR1(I2C1)
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#define I2C2_OAR1 I2C_OAR1(I2C2)
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/* Own address register 2 (I2Cx_OAR2) */
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#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c)
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#define I2C1_OAR2 I2C_OAR2(I2C1)
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#define I2C2_OAR2 I2C_OAR2(I2C2)
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#ifdef STM32F3
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/**@{*/
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/* Timing register (I2Cx_TIMINGR) */
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#define I2C_TIMINGR(i2c_base) MMIO32(i2c_base + 0x10)
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#define I2C1_TIMINGR I2C_TIMINGR(I2C1)
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#define I2C2_TIMINGR I2C_TIMINGR(I2C2)
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/* Timeout register (I2Cx_TIMEOUTR) */
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#define I2C_TIMEOUTR(i2c_base) MMIO32(i2c_base + 0x14)
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#define I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1)
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#define I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2)
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/* Interrupt and Status register (I2Cx_ISR) */
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#define I2C_ISR(i2c_base) MMIO32(i2c_base + 0x18)
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#define I2C1_ISR I2C_ISR(I2C1)
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#define I2C2_ISR I2C_ISR(I2C2)
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/* Interrupt clear register (I2Cx_ICR) */
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#define I2C_ICR(i2c_base) MMIO32(i2c_base + 0x1C)
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#define I2C1_ICR I2C_ICR(I2C1)
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#define I2C2_ICR I2C_ICR(I2C2)
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/* PEC register (I2Cx_PECR) */
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#define I2C_PECR(i2c_base) MMIO32(i2c_base + 0x20)
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#define I2C1_PECR I2C_PECR(I2C1)
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#define I2C2_PECR I2C_PECR(I2C2)
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/* Receive data register (I2Cx_RXDR) */
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#define I2C_RXDR(i2c_base) MMIO32(i2c_base + 0x24)
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#define I2C1_RXDR I2C_RXDR(I2C1)
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#define I2C2_RXDR I2C_RXDR(I2C2)
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/* Transmit data register (I2Cx_TXDR) */
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#define I2C_TXDR(i2c_base) MMIO32(i2c_base + 0x28)
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#define I2C1_TXDR I2C_TXDR(I2C1)
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#define I2C2_TXDR I2C_TXDR(I2C2)
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/* --- I2Cx_CR1 values ----------------------------------------------------- */
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/* PECEN: PEC enable */
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#define I2C_CR1_PECEN (1 << 23)
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/* ALERTEN: SMBus alert enable */
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#define I2C_CR1_ALERTEN (1 << 22)
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/* SMBDEN: SMBus Device Default address enable */
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#define I2C_CR1_SMBDEN (1 << 21)
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/* SMBHEN: SMBus Host address enable */
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#define I2C_CR1_SMBHEN (1 << 20)
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/* GCEN: General call enable */
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#define I2C_CR1_GCEN (1 << 19)
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/* WUPEN: Wakeup from STOP enable */
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#define I2C_CR1_WUPEN (1 << 18)
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/* NOSTRETCH: Clock stretching disable */
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#define I2C_CR1_NOSTRETCH (1 << 17)
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/* SBC: Slave byte control */
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#define I2C_CR1_SBC (1 << 16)
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/* RXDMAEN: DMA reception requests enable */
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#define I2C_CR1_RXDMAEN (1 << 15)
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/* TXDMAEN: DMA transmission requests enable */
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#define I2C_CR1_TXDMAEN (1 << 14)
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/* ANFOFF: Analog noise filter OFF */
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#define I2C_CR1_ANFOFF (1 << 12)
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/* DNF[3:0]: Digital noise filter */
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#define I2C_CR1_DNF_DISABLED (0x0 << 8)
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#define I2C_CR1_DNF_UP_1_TI2CCLK (0x1 << 8)
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#define I2C_CR1_DNF_UP_2_TI2CCLK (0x2 << 8)
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#define I2C_CR1_DNF_UP_3_TI2CCLK (0x3 << 8)
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#define I2C_CR1_DNF_UP_4_TI2CCLK (0x4 << 8)
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#define I2C_CR1_DNF_UP_5_TI2CCLK (0x5 << 8)
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#define I2C_CR1_DNF_UP_6_TI2CCLK (0x6 << 8)
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#define I2C_CR1_DNF_UP_7_TI2CCLK (0x7 << 8)
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#define I2C_CR1_DNF_UP_8_TI2CCLK (0x8 << 8)
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#define I2C_CR1_DNF_UP_9_TI2CCLK (0x9 << 8)
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#define I2C_CR1_DNF_UP_10_TI2CCLK (0xA << 8)
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#define I2C_CR1_DNF_UP_11_TI2CCLK (0xB << 8)
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#define I2C_CR1_DNF_UP_12_TI2CCLK (0xC << 8)
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#define I2C_CR1_DNF_UP_13_TI2CCLK (0xD << 8)
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#define I2C_CR1_DNF_UP_14_TI2CCLK (0xE << 8)
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#define I2C_CR1_DNF_UP_15_TI2CCLK (0xF << 8)
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/* ERRIE: Error interrupts enable */
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#define I2C_CR1_ERRIE (1 << 7)
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/* TCIE: Transfer Complete interrupt enable */
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#define I2C_CR1_TCIE (1 << 6)
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/* STOPIE: STOP detection Interrupt enable */
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#define I2C_CR1_STOPIE (1 << 5)
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/* NACKIE: Not acknowledge received Interrupt enable */
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#define I2C_CR1_NACKIE (1 << 4)
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/* ADDRIE: Address match Interrupt enable (slave only) */
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#define I2C_CR1_DDRIE (1 << 3)
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/* RXIE: RX Interrupt enable */
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#define I2C_CR1_RXIE (1 << 2)
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/* TXIE: TX Interrupt enable */
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#define I2C_CR1_TXIE (1 << 1)
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/* PE: Peripheral enable */
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#define I2C_CR1_PE (1 << 0)
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/* --- I2Cx_CR2 values ----------------------------------------------------- */
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/* PECBYTE: Packet error checking byte */
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#define I2C_CR2_PECBYTE (1 << 26)
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/* AUTOEND: Automatic end mode (master mode) */
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#define I2C_CR2_AUTOEND (1 << 25)
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/* RELOAD: NBYTES reload mode */
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#define I2C_CR2_RELOAD (1 << 24)
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/* NBYTES[7:0]: Number of bytes (23,16) */
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/* NACK: NACK generation (slave mode) */
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#define I2C_CR2_NACK (1 << 15)
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/* STOP: Stop generation (master mode) */
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#define I2C_CR2_STOP (1 << 14)
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/* START: Start generation */
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#define I2C_CR2_START (1 << 13)
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/* HEAD10R: 10-bit address header only read direction (master receiver mode) */
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#define I2C_CR2_HEAD10R (1 << 12)
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/* ADD10: 10-bit addressing mode (master mode) */
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#define I2C_CR2_ADD10 (1 << 11)
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/* RD_WRN: Transfer direction (master mode) */
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#define I2C_CR2_RD_WRN (1 << 10)
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//preguntar
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/* SADD[9:8]: Slave address bit 9:8 (master mode) */
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#define I2C_CR2_SADD1_7BIT (0x0 << 8)
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#define I2C_CR2_SADD1_10BIT (0x1 << 8)
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/* SADD[7:1]: Slave address bit 7:1 (master mode) */
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#define I2C_CR2_SADD2_7BIT (0x0 << 1)
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#define I2C_CR2_SADD2_10BIT (0x1 << 1)
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/* SADD0: Slave address bit 0 (master mode) */
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#define I2C_CR2_SADD0_7BIT (0 << 0)
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#define I2C_CR2_SADD0_10BIT (1 << 0)
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/* --- I2Cx_OAR1 values ---------------------------------------------------- */
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/* OA1EN: Own Address 1 enable */
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#define I2C_OAR1_OA1EN_DISABLE (0x0 << 15)
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#define I2C_OAR1_OA1EN_ENABLE (0x1 <<15)
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/* OA1MODE Own Address 1 10-bit mode */
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#define I2C_OAR1_OA1MODE (1 << 10)
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#define I2C_OAR1_OA1MODE_7BIT 0
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#define I2C_OAR1_OA1MODE_10BIT 1
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//preguntar
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/* OA1[9:8]: Interface address */
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/* OA1[7:1]: Interface address */
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/* OA1[0]: Interface address */
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#define I2C_OAR1_OA1 (1 << 10)
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#define I2C_OAR1_OA1_7BIT 0
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#define I2C_OAR1_OA1_10BIT 1
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/* --- I2Cx_OAR2 values ---------------------------------------------------- */
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/* OA2EN: Own Address 2 enable */
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#define I2C_OAR2_OA2EN (1 << 15)
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/* OA2MSK[2:0]: Own Address 2 masks */
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#define I2C_OAR2_OA2MSK_NO_MASK (0x0 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7_OA2_2 (0x1 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7_OA2_3 (0x2 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7_OA2_4 (0x3 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7_OA2_5 (0x4 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7_OA2_6 (0x5 << 8)
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#define I2C_OAR2_OA2MSK_OA2_7 (0x6 << 8)
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#define I2C_OAR2_OA2MSK_NO_CMP (0x7 << 8)
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/* OA2[7:1]: Interface address */
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/* --- I2Cx_TIMINGR values ---------------------------------------------------- */
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//Not clear yet.
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/* PRESC[3:0]: Timing prescaler (31,28) */
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/* SCLDEL[3:0]: Data setup time (23,20) */
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/* SDADEL[3:0]: Data hold time (19,16) */
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/* SCLH[7:0]: SCL high period (master mode) (15,8) */
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/* SCLL[7:0]: SCL low period (master mode) (7,0) */
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/* --- I2Cx_TIEMOUTR values ---------------------------------------------------- */
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/* TEXTEN: Extended clock timeout enable */
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#define I2C_TIEMOUTR_TEXTEN (1 << 31)
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//Not clear yet.
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/* TIMEOUTB[11:0]: Bus timeout B */
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/* TIMOUTEN: Clock timeout enable */
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#define I2C_TIEMOUTR_TIMOUTEN (1 << 15)
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/* TIDLE: Idle clock timeout detection */
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#define I2C_TIEMOUTR_TIDLE_SCL_LOW (0x0 << 12)
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#define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH (0x1 << 12)
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//Not clear yet.
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/* TIMEOUTA[11:0]: Bus Timeout A */
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/* --- I2Cx_ISR values ---------------------------------------------------- */
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/* Bits 31:24 Reserved, must be kept at reset value */
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//Not clear yet.
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/* ADDCODE[6:0]: Address match code (Slave mode) */
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/* DIR: Transfer direction (Slave mode) */
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#define I2C_ISR_DIR_READ (0x1 << 16)
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#define I2C_ISR_DIR_WRITE (0x0 << 16)
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/* BUSY: Bus busy */
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#define I2C_ISR_BUSY (1 << 15)
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/* ALERT: SMBus alert */
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#define I2C_ISR_ALERT (1 << 13)
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/* TIMEOUT: Timeout or tLOW detection flag */
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#define I2C_ISR_TIMEOUT (1 << 12)
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/* PECERR: PEC Error in reception */
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#define I2C_ISR_PECERR (1 << 11)
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/* OVR: Overrun/Underrun (slave mode) */
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#define I2C_ISR_OVR (1 << 10)
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/* ARLO: Arbitration lost */
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#define I2C_ISR_ARLO (1 << 9)
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/* BERR: Bus error */
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#define I2C_ISR_BERR (1 << 8)
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/* TCR: Transfer Complete Reload */
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#define I2C_ISR_TCR (1 << 7)
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/* TC: Transfer Complete (master mode) */
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#define I2C_ISR_TC (1 << 6)
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/* STOPF: Stop detection flag */
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#define I2C_ISR_STOPF (1 << 5)
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/* NACKF: Not Acknowledge received flag */
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#define I2C_ISR_NACKF (1 << 4)
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/* ADDR: Address matched (slave mode) */
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#define I2C_ISR_ADDR (1 << 3)
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/* RXNE: Receive data register not empty (receivers) */
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#define I2C_ISR_RXNE (1 << 2)
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/* TXIS: Transmit interrupt status (transmitters) */
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#define I2C_ISR_TXIS (1 << 1)
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/* TXE: Transmit data register empty (transmitters) */
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#define I2C_ISR_TXE (1 << 0)
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/* --- I2Cx_ICR values ---------------------------------------------------- */
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/* ALERTCF: Alert flag clear */
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#define I2C_ICR_ALERTCF (1 << 13)
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/* TIMOUTCF: Timeout detection flag clear */
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#define I2C_ICR_TIMOUTCF (1 << 12)
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/* PECCF: PEC Error flag clear */
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#define I2C_ICR_PECCF (1 << 11)
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/* OVRCF: Overrun/Underrun flag clear */
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#define I2C_ICR_OVRCF (1 << 10)
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/* ARLOCF: Arbitration Lost flag clear */
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#define I2C_ICR_ARLOCF (1 << 9)
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/* BERRCF: Bus error flag clear */
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#define I2C_ICR_BERRCF (1 << 8)
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/* STOPCF: Stop detection flag clear */
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#define I2C_ICR_STOPCF (1 << 5)
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/* NACKCF: Not Acknowledge flag clear */
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#define I2C_ICR_NACKCF (1 << 4)
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/* ADDRCF: Address Matched flag clear */
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#define I2C_ICR_ADDRCF (1 << 3)
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/* --- I2Cx_PECR values ---------------------------------------------------- */
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/* PEC[7:0] Packet error checking register */
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/* --- I2Cx_RXDR values ---------------------------------------------------- */
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/* RXDATA[7:0] 8-bit receive data */
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/* --- I2Cx_TXDR values ---------------------------------------------------- */
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/* TXDATA[7:0] 8-bit transmit data */
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#else
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/* Data register (I2Cx_DR) */
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#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10)
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#define I2C1_DR I2C_DR(I2C1)
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#define I2C2_DR I2C_DR(I2C2)
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/* Status register 1 (I2Cx_SR1) */
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#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14)
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#define I2C1_SR1 I2C_SR1(I2C1)
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#define I2C2_SR1 I2C_SR1(I2C2)
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/* Status register 2 (I2Cx_SR2) */
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#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18)
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#define I2C1_SR2 I2C_SR2(I2C1)
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#define I2C2_SR2 I2C_SR2(I2C2)
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/* Clock control register (I2Cx_CCR) */
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#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c)
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#define I2C1_CCR I2C_CCR(I2C1)
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#define I2C2_CCR I2C_CCR(I2C2)
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/* TRISE register (I2Cx_CCR) */
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#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20)
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#define I2C1_TRISE I2C_TRISE(I2C1)
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#define I2C2_TRISE I2C_TRISE(I2C2)
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/* --- I2Cx_CR1 values ----------------------------------------------------- */
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/* SWRST: Software reset */
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#define I2C_CR1_SWRST (1 << 15)
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/* Note: Bit 14 is reserved, and forced to 0 by hardware. */
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/* ALERT: SMBus alert */
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#define I2C_CR1_ALERT (1 << 13)
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/* PEC: Packet error checking */
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#define I2C_CR1_PEC (1 << 12)
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/* POS: Acknowledge / PEC position */
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#define I2C_CR1_POS (1 << 11)
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/* ACK: Acknowledge enable */
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#define I2C_CR1_ACK (1 << 10)
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/* STOP: STOP generation */
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#define I2C_CR1_STOP (1 << 9)
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/* START: START generation */
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#define I2C_CR1_START (1 << 8)
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/* NOSTRETCH: Clock stretching disable (slave mode) */
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#define I2C_CR1_NOSTRETCH (1 << 7)
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/* ENGC: General call enable */
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#define I2C_CR1_ENGC (1 << 6)
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/* ENPEC: Enable PEC */
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#define I2C_CR1_ENPEC (1 << 5)
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/* ENARP: ARP enable */
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#define I2C_CR1_ENARP (1 << 4)
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/* SMBTYPE: SMBus type */
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#define I2C_CR1_SMBTYPE (1 << 3)
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/* Note: Bit 2 is reserved, and forced to 0 by hardware. */
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/* SMBUS: SMBus mode */
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#define I2C_CR1_SMBUS (1 << 1)
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/* PE: Peripheral enable */
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#define I2C_CR1_PE (1 << 0)
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/* --- I2Cx_CR2 values ----------------------------------------------------- */
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/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */
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/* LAST: DMA last transfer */
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#define I2C_CR2_LAST (1 << 12)
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/* DMAEN: DMA requests enable */
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#define I2C_CR2_DMAEN (1 << 11)
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/* ITBUFEN: Buffer interrupt enable */
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#define I2C_CR2_ITBUFEN (1 << 10)
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/* ITEVTEN: Event interrupt enable */
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#define I2C_CR2_ITEVTEN (1 << 9)
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/* ITERREN: Error interrupt enable */
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#define I2C_CR2_ITERREN (1 << 8)
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/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
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/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
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/****************************************************************************/
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/** @defgroup i2c_clock I2C clock frequency settings
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@ingroup i2c_defines
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@{*/
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#define I2C_CR2_FREQ_2MHZ 0x02
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#define I2C_CR2_FREQ_3MHZ 0x03
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#define I2C_CR2_FREQ_4MHZ 0x04
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#define I2C_CR2_FREQ_5MHZ 0x05
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#define I2C_CR2_FREQ_6MHZ 0x06
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#define I2C_CR2_FREQ_7MHZ 0x07
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#define I2C_CR2_FREQ_8MHZ 0x08
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#define I2C_CR2_FREQ_9MHZ 0x09
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#define I2C_CR2_FREQ_10MHZ 0x0a
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#define I2C_CR2_FREQ_11MHZ 0x0b
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#define I2C_CR2_FREQ_12MHZ 0x0c
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#define I2C_CR2_FREQ_13MHZ 0x0d
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#define I2C_CR2_FREQ_14MHZ 0x0e
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#define I2C_CR2_FREQ_15MHZ 0x0f
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#define I2C_CR2_FREQ_16MHZ 0x10
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#define I2C_CR2_FREQ_17MHZ 0x11
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#define I2C_CR2_FREQ_18MHZ 0x12
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#define I2C_CR2_FREQ_19MHZ 0x13
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#define I2C_CR2_FREQ_20MHZ 0x14
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#define I2C_CR2_FREQ_21MHZ 0x15
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#define I2C_CR2_FREQ_22MHZ 0x16
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#define I2C_CR2_FREQ_23MHZ 0x17
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#define I2C_CR2_FREQ_24MHZ 0x18
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#define I2C_CR2_FREQ_25MHZ 0x19
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#define I2C_CR2_FREQ_26MHZ 0x1a
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#define I2C_CR2_FREQ_27MHZ 0x1b
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#define I2C_CR2_FREQ_28MHZ 0x1c
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#define I2C_CR2_FREQ_29MHZ 0x1d
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#define I2C_CR2_FREQ_30MHZ 0x1e
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#define I2C_CR2_FREQ_31MHZ 0x1f
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#define I2C_CR2_FREQ_32MHZ 0x20
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#define I2C_CR2_FREQ_33MHZ 0x21
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#define I2C_CR2_FREQ_34MHZ 0x22
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#define I2C_CR2_FREQ_35MHZ 0x23
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#define I2C_CR2_FREQ_36MHZ 0x24
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/**@}*/
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/* --- I2Cx_OAR1 values ---------------------------------------------------- */
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/* ADDMODE: Addressing mode (slave mode) */
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#define I2C_OAR1_ADDMODE (1 << 15)
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#define I2C_OAR1_ADDMODE_7BIT 0
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#define I2C_OAR1_ADDMODE_10BIT 1
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/* Note: Bit 14 should always be kept at 1 by software! */
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/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */
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/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */
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/* --- I2Cx_OAR2 values ---------------------------------------------------- */
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/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
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/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */
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/* ENDUAL: Dual addressing mode enable */
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#define I2C_OAR2_ENDUAL (1 << 0)
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/* --- I2Cx_DR values ------------------------------------------------------ */
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/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
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/* DR[7:0] 8-bit data register */
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/* --- I2Cx_SR1 values ----------------------------------------------------- */
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/* SMBALERT: SMBus alert */
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#define I2C_SR1_SMBALERT (1 << 15)
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/* TIMEOUT: Timeout or Tlow Error */
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#define I2C_SR1_TIMEOUT (1 << 14)
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/* Note: Bit 13 is reserved, and forced to 0 by hardware. */
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|
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/* PECERR: PEC Error in reception */
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#define I2C_SR1_PECERR (1 << 12)
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/* OVR: Overrun/Underrun */
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#define I2C_SR1_OVR (1 << 11)
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/* AF: Acknowledge failure */
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|
#define I2C_SR1_AF (1 << 10)
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/* ARLO: Arbitration lost (master mode) */
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#define I2C_SR1_ARLO (1 << 9)
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/* BERR: Bus error */
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#define I2C_SR1_BERR (1 << 8)
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/* TxE: Data register empty (transmitters) */
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#define I2C_SR1_TxE (1 << 7)
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/* RxNE: Data register not empty (receivers) */
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#define I2C_SR1_RxNE (1 << 6)
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/* Note: Bit 5 is reserved, and forced to 0 by hardware. */
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|
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/* STOPF: STOP detection (slave mode) */
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|
#define I2C_SR1_STOPF (1 << 4)
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/* ADD10: 10-bit header sent (master mode) */
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|
#define I2C_SR1_ADD10 (1 << 3)
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|
|
/* BTF: Byte transfer finished */
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|
#define I2C_SR1_BTF (1 << 2)
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|
/* ADDR: Address sent (master mode) / address matched (slave mode) */
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|
#define I2C_SR1_ADDR (1 << 1)
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|
|
|
/* SB: Start bit (master mode) */
|
|
#define I2C_SR1_SB (1 << 0)
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|
|
|
/* --- I2Cx_SR2 values ----------------------------------------------------- */
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|
|
|
/* Bits [15:8]: PEC[7:0]: Packet error checking register */
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|
|
|
/* DUALF: Dual flag (slave mode) */
|
|
#define I2C_SR2_DUALF (1 << 7)
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|
|
|
/* SMBHOST: SMBus host header (slave mode) */
|
|
#define I2C_SR2_SMBHOST (1 << 6)
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|
|
|
/* SMBDEFAULT: SMBus device default address (slave mode) */
|
|
#define I2C_SR2_SMBDEFAULT (1 << 5)
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|
|
|
/* GENCALL: General call address (slave mode) */
|
|
#define I2C_SR2_GENCALL (1 << 4)
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|
|
|
/* Note: Bit 3 is reserved, and forced to 0 by hardware. */
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|
|
|
/* TRA: Transmitter / receiver */
|
|
#define I2C_SR2_TRA (1 << 2)
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|
|
|
/* BUSY: Bus busy */
|
|
#define I2C_SR2_BUSY (1 << 1)
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|
|
|
/* MSL: Master / slave */
|
|
#define I2C_SR2_MSL (1 << 0)
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|
|
|
/* --- I2Cx_CCR values ----------------------------------------------------- */
|
|
|
|
/* F/S: I2C Master mode selection (fast / standard) */
|
|
#define I2C_CCR_FS (1 << 15)
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|
|
|
/* DUTY: Fast Mode Duty Cycle */
|
|
/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles
|
|
@ingroup i2c_defines
|
|
|
|
@{*/
|
|
#define I2C_CCR_DUTY (1 << 14)
|
|
#define I2C_CCR_DUTY_DIV2 0
|
|
#define I2C_CCR_DUTY_16_DIV_9 1
|
|
/**@}*/
|
|
|
|
/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
|
|
|
|
/*
|
|
* Bits [11:0]:
|
|
* CCR[11:0]: Clock control register in Fast/Standard mode (master mode)
|
|
*/
|
|
|
|
/* --- I2Cx_TRISE values --------------------------------------------------- */
|
|
|
|
/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
|
|
|
|
/*
|
|
* Bits [5:0]:
|
|
* TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
|
|
*/
|
|
|
|
#endif
|
|
|
|
/* --- I2C constant definitions -------------------------------------------- */
|
|
|
|
/****************************************************************************/
|
|
/** @defgroup i2c_rw I2C Read/Write bit
|
|
@ingroup i2c_defines
|
|
|
|
@{*/
|
|
#define I2C_WRITE 0
|
|
#define I2C_READ 1
|
|
/**@}*/
|
|
|
|
/* --- I2C function prototypes---------------------------------------------- */
|
|
|
|
/* void i2c_reset(uint32_t i2c); */
|
|
/* void i2c_peripheral_enable(uint32_t i2c); */
|
|
/* void i2c_peripheral_disable(uint32_t i2c); */
|
|
/* void i2c_send_start(uint32_t i2c); */
|
|
/* void i2c_send_stop(uint32_t i2c); */
|
|
/* void i2c_clear_stop(uint32_t i2c); */
|
|
/* void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave); */
|
|
/* void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave); */
|
|
/* void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq); */
|
|
/* void i2c_send_data(uint32_t i2c, uint8_t data); */
|
|
|
|
BEGIN_DECLS
|
|
|
|
void i2c_reset(uint32_t i2c);
|
|
void i2c_peripheral_enable(uint32_t i2c);
|
|
void i2c_peripheral_disable(uint32_t i2c);
|
|
void i2c_send_start(uint32_t i2c);
|
|
void i2c_send_stop(uint32_t i2c);
|
|
void i2c_clear_stop(uint32_t i2c);
|
|
void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave);
|
|
void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave);
|
|
void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq);
|
|
void i2c_send_data(uint32_t i2c, uint8_t data);
|
|
|
|
#ifndef STM32F3
|
|
|
|
void i2c_set_fast_mode(uint32_t i2c);
|
|
void i2c_set_standard_mode(uint32_t i2c);
|
|
void i2c_set_ccr(uint32_t i2c, uint16_t freq);
|
|
void i2c_set_trise(uint32_t i2c, uint16_t trise);
|
|
void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite);
|
|
uint8_t i2c_get_data(uint32_t i2c);
|
|
void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt);
|
|
void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt);
|
|
void i2c_enable_ack(uint32_t i2c);
|
|
void i2c_disable_ack(uint32_t i2c);
|
|
void i2c_nack_next(uint32_t i2c);
|
|
void i2c_nack_current(uint32_t i2c);
|
|
void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle);
|
|
void i2c_enable_dma(uint32_t i2c);
|
|
void i2c_disable_dma(uint32_t i2c);
|
|
void i2c_set_dma_last_transfer(uint32_t i2c);
|
|
void i2c_clear_dma_last_transfer(uint32_t i2c);
|
|
|
|
#endif
|
|
|
|
END_DECLS
|
|
|
|
#endif
|
|
/** @cond */
|
|
#else
|
|
#warning "i2c_common_all.h should not be included explicitly, only via i2c.h"
|
|
#endif
|
|
/** @endcond */
|
|
/**@}*/
|
|
|