546 lines
18 KiB
C
546 lines
18 KiB
C
/** @addtogroup adc_defines
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@author @htmlonly © @endhtmlonly 2014 Karl Palsson <karlp@tweak.net.au>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Matthew Lai <m@matthewlai.ca>
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* Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H
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The order of header inclusion is important. adc.h includes the device
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specific memorymap.h header before including this header file.*/
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/*
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* Common code for F4 and F7 ADCs. The only differences are in external trigger
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* setup (see AN4660).
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*/
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/** @cond */
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#ifdef LIBOPENCM3_ADC_H
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/** @endcond */
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#ifndef LIBOPENCM3_ADC_COMMON_V3_H
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#define LIBOPENCM3_ADC_COMMON_V3_H
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#include <libopencm3/stm32/common/adc_common_v1.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */
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#define ADC_JOFR1(block) MMIO32((block) + 0x14)
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#define ADC_JOFR2(block) MMIO32((block) + 0x18)
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#define ADC_JOFR3(block) MMIO32((block) + 0x1c)
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#define ADC_JOFR4(block) MMIO32((block) + 0x20)
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/* ADC watchdog high threshold register (ADC_HTR) */
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#define ADC_HTR(block) MMIO32((block) + 0x24)
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/* ADC watchdog low threshold register (ADC_LTR) */
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#define ADC_LTR(block) MMIO32((block) + 0x28)
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/* ADC regular sequence register 1 (ADC_SQR1) */
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#define ADC_SQR1(block) MMIO32((block) + 0x2c)
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/* ADC regular sequence register 2 (ADC_SQR2) */
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#define ADC_SQR2(block) MMIO32((block) + 0x30)
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/* ADC regular sequence register 3 (ADC_SQR3) */
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#define ADC_SQR3(block) MMIO32((block) + 0x34)
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/* ADC injected sequence register (ADC_JSQR) */
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#define ADC_JSQR(block) MMIO32((block) + 0x38)
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/* ADC injected data register x (ADC_JDRx) (x=1..4) */
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#define ADC_JDR1(block) MMIO32((block) + 0x3c)
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#define ADC_JDR2(block) MMIO32((block) + 0x40)
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#define ADC_JDR3(block) MMIO32((block) + 0x44)
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#define ADC_JDR4(block) MMIO32((block) + 0x48)
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/* ADC regular data register (ADC_DR) */
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#define ADC_DR(block) MMIO32((block) + 0x4c)
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/* ADC common (shared) registers */
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#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300)
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#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0)
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#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4)
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#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8)
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/* --- ADC Channels ------------------------------------------------------- */
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/** @defgroup adc_channel ADC Channel Numbers
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* @ingroup adc_defines
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* Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18!
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*@{*/
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#define ADC_CHANNEL_TEMP_F40 16
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#define ADC_CHANNEL_TEMP_F42 18
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#define ADC_CHANNEL_VREF 17
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#define ADC_CHANNEL_VBAT 18
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/**@}*/
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/* --- ADC_SR values ------------------------------------------------------- */
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/** @defgroup adc_sr_values ADC Status Register Flags
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* @ingroup adc_defines
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*@{*/
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/* OVR:*//** Overrun */
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#define ADC_SR_OVR (1 << 5)
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/**@}*/
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/* --- ADC_CR1 values specific to STM32F2,4--------------------------------- */
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/* OVRIE: Overrun interrupt enable */
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#define ADC_CR1_OVRIE (1 << 26)
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/* RES[1:0]: Resolution */
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/****************************************************************************/
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/** @defgroup adc_cr1_res ADC Resolution.
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@ingroup adc_defines
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@{*/
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#define ADC_CR1_RES_12BIT (0x0 << 24)
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#define ADC_CR1_RES_10BIT (0x1 << 24)
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#define ADC_CR1_RES_8BIT (0x2 << 24)
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#define ADC_CR1_RES_6BIT (0x3 << 24)
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/**@}*/
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#define ADC_CR1_RES_MASK (0x3 << 24)
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#define ADC_CR1_RES_SHIFT 24
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/* Note: Bits [21:16] are reserved, and must be kept at reset value. */
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/* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */
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#define ADC_CR1_AWDCH_MAX 18
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/* --- ADC_CR2 values ------------------------------------------------------ */
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/* SWSTART: Start conversion of regular channels. */
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#define ADC_CR2_SWSTART (1 << 30)
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/* EXTEN[1:0]: External trigger enable for regular channels. */
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/****************************************************************************/
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/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity
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@ingroup adc_defines
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@{*/
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#define ADC_CR2_EXTEN_DISABLED (0x0 << 28)
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#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << 28)
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#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << 28)
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#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << 28)
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/**@}*/
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#define ADC_CR2_EXTEN_MASK (0x3 << 28)
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#define ADC_CR2_EXTEN_SHIFT 28
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/* EXTSEL[3:0]: External event selection for regular group. */
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/****************************************************************************/
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/* Note: Selection values are family-dependent. */
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#define ADC_CR2_EXTSEL_MASK (0xF << 24)
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#define ADC_CR2_EXTSEL_SHIFT 24
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/* Bit 23 is reserved */
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/* JSWSTART: Start conversion of injected channels. */
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#define ADC_CR2_JSWSTART (1 << 22)
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/* JEXTEN[1:0]: External trigger enable for injected channels. */
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/****************************************************************************/
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/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity
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@ingroup adc_defines
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@{*/
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#define ADC_CR2_JEXTEN_DISABLED (0x0 << 20)
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#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << 20)
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#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << 20)
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#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << 20)
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/**@}*/
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#define ADC_CR2_JEXTEN_MASK (0x3 << 20)
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#define ADC_CR2_JEXTEN_SHIFT 20
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/* JEXTSEL[3:0]: External event selection for injected group. */
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/****************************************************************************/
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/* Note: Selection values are family-dependent. */
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#define ADC_CR2_JEXTSEL_MASK (0xF << 16)
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#define ADC_CR2_JEXTSEL_SHIFT 16
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/* ALIGN: Data alignement. */
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#define ADC_CR2_ALIGN_RIGHT (0 << 11)
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#define ADC_CR2_ALIGN_LEFT (1 << 11)
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#define ADC_CR2_ALIGN (1 << 11)
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/* EOCS: End of conversion selection. */
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#define ADC_CR2_EOCS (1 << 10)
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/* DDS: DMA disable selection */
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#define ADC_CR2_DDS (1 << 9)
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/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */
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#define ADC_CR2_DMA (1 << 8)
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/* Note: Bits [7:2] are reserved and must be kept at reset value. */
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/* CONT: Continuous conversion. */
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#define ADC_CR2_CONT (1 << 1)
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/* ADON: A/D converter On/Off. */
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/* Note: If any other bit in this register apart from ADON is changed at the
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* same time, then conversion is not triggered. This is to prevent triggering
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* an erroneous conversion.
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* Conclusion: Must be separately written.
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*/
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#define ADC_CR2_ADON (1 << 0)
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/* --- ADC_SMPR1 values ---------------------------------------------------- */
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#define ADC_SMPR1_SMP17_LSB 21
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#define ADC_SMPR1_SMP16_LSB 18
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#define ADC_SMPR1_SMP15_LSB 15
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#define ADC_SMPR1_SMP14_LSB 12
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#define ADC_SMPR1_SMP13_LSB 9
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#define ADC_SMPR1_SMP12_LSB 6
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#define ADC_SMPR1_SMP11_LSB 3
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#define ADC_SMPR1_SMP10_LSB 0
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#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMPR1_SMP17_LSB)
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#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMPR1_SMP16_LSB)
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#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMPR1_SMP15_LSB)
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#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMPR1_SMP14_LSB)
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#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMPR1_SMP13_LSB)
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#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMPR1_SMP12_LSB)
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#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMPR1_SMP11_LSB)
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#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMPR1_SMP10_LSB)
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/* --- ADC_SMPR2 values ---------------------------------------------------- */
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#define ADC_SMPR2_SMP9_LSB 27
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#define ADC_SMPR2_SMP8_LSB 24
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#define ADC_SMPR2_SMP7_LSB 21
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#define ADC_SMPR2_SMP6_LSB 18
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#define ADC_SMPR2_SMP5_LSB 15
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#define ADC_SMPR2_SMP4_LSB 12
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#define ADC_SMPR2_SMP3_LSB 9
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#define ADC_SMPR2_SMP2_LSB 6
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#define ADC_SMPR2_SMP1_LSB 3
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#define ADC_SMPR2_SMP0_LSB 0
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#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMPR2_SMP9_LSB)
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#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMPR2_SMP8_LSB)
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#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMPR2_SMP7_LSB)
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#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMPR2_SMP6_LSB)
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#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMPR2_SMP5_LSB)
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#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMPR2_SMP4_LSB)
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#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMPR2_SMP3_LSB)
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#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMPR2_SMP2_LSB)
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#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMPR2_SMP1_LSB)
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#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMPR2_SMP0_LSB)
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/* --- ADC_SMPRx values --------------------------------------------------- */
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/****************************************************************************/
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/* ADC_SMPRG ADC Sample Time Selection for Channels */
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/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
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@ingroup adc_defines
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@{*/
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#define ADC_SMPR_SMP_3CYC 0x0
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#define ADC_SMPR_SMP_15CYC 0x1
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#define ADC_SMPR_SMP_28CYC 0x2
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#define ADC_SMPR_SMP_56CYC 0x3
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#define ADC_SMPR_SMP_84CYC 0x4
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#define ADC_SMPR_SMP_112CYC 0x5
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#define ADC_SMPR_SMP_144CYC 0x6
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#define ADC_SMPR_SMP_480CYC 0x7
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/**@}*/
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/* --- ADC_SQR1 values ----------------------------------------------------- */
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#define ADC_SQR_MAX_CHANNELS_REGULAR 16
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#define ADC_SQR1_SQ16_LSB 15
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#define ADC_SQR1_SQ15_LSB 10
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#define ADC_SQR1_SQ14_LSB 5
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#define ADC_SQR1_SQ13_LSB 0
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#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
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#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
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#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
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#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
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#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
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/* --- ADC_SQR2 values ----------------------------------------------------- */
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#define ADC_SQR2_SQ12_LSB 25
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#define ADC_SQR2_SQ11_LSB 20
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#define ADC_SQR2_SQ10_LSB 15
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#define ADC_SQR2_SQ9_LSB 10
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#define ADC_SQR2_SQ8_LSB 5
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#define ADC_SQR2_SQ7_LSB 0
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#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
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#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
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#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
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#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
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#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
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#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
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/* --- ADC_SQR3 values ----------------------------------------------------- */
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#define ADC_SQR3_SQ6_LSB 25
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#define ADC_SQR3_SQ5_LSB 20
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#define ADC_SQR3_SQ4_LSB 15
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#define ADC_SQR3_SQ3_LSB 10
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#define ADC_SQR3_SQ2_LSB 5
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#define ADC_SQR3_SQ1_LSB 0
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#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
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#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
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#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
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#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
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#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
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#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
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/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
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#define ADC_JDATA_LSB 0
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#define ADC_DATA_LSB 0
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#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB)
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#define ADC_DATA_MSK (0xffff << ADC_DA)
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/* --- Common Registers ---------------------------------------------------- */
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/* --- ADC_CSR values (read only images) ------------------------------------ */
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/* OVR3: Overrun ADC3. */
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#define ADC_CSR_OVR3 (1 << 21)
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/* STRT3: Regular channel start ADC3. */
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#define ADC_CSR_STRT3 (1 << 20)
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/* JSTRT3: Injected channel start ADC3. */
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#define ADC_CSR_JSTRT3 (1 << 19)
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/* JEOC3: Injected channel end of conversion ADC3. */
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#define ADC_CSR_JEOC3 (1 << 18)
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/* EOC3: Regular channel end of conversion ADC3. */
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#define ADC_CSR_EOC3 (1 << 17)
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/* EOC3: Regular channel end of conversion ADC3. */
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#define ADC_CSR_AWD3 (1 << 16)
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/* Bits 15:14 Reserved, must be kept at reset value */
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/* OVR2: Overrun ADC2. */
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#define ADC_CSR_OVR2 (1 << 13)
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/* STRT2: Regular channel start ADC2. */
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#define ADC_CSR_STRT2 (1 << 12)
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/* JSTRT2: Injected channel start ADC2. */
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#define ADC_CSR_JSTRT2 (1 << 11)
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/* JEOC2: Injected channel end of conversion ADC2. */
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#define ADC_CSR_JEOC2 (1 << 10)
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/* EOC2: Regular channel end of conversion ADC2. */
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#define ADC_CSR_EOC2 (1 << 9)
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/* EOC2: Regular channel end of conversion ADC2. */
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#define ADC_CSR_AWD2 (1 << 8)
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/* Bits 7:6 Reserved, must be kept at reset value */
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/* OVR1: Overrun ADC1. */
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#define ADC_CSR_OVR1 (1 << 5)
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/* STRT1: Regular channel start ADC1. */
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#define ADC_CSR_STRT1 (1 << 4)
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/* JSTRT1: Injected channel start ADC1. */
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#define ADC_CSR_JSTRT1 (1 << 3)
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/* JEOC1: Injected channel end of conversion ADC1. */
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#define ADC_CSR_JEOC1 (1 << 2)
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/* EOC1: Regular channel end of conversion ADC1. */
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#define ADC_CSR_EOC1 (1 << 1)
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/* EOC1: Regular channel end of conversion ADC1. */
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#define ADC_CSR_AWD1 (1 << 0)
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/* --- ADC_CCR values ------------------------------------------------------ */
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/* TSVREFE: Temperature sensor and Vrefint enable. */
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#define ADC_CCR_TSVREFE (1 << 23)
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/* VBATE: VBat enable. */
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#define ADC_CCR_VBATE (1 << 22)
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/* Bit 18:21 reserved, must be kept at reset value. */
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/* ADCPRE: ADC prescaler. */
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/****************************************************************************/
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/** @defgroup adc_ccr_adcpre ADC Prescale
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@ingroup adc_defines
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@{*/
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#define ADC_CCR_ADCPRE_BY2 (0x0 << 16)
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#define ADC_CCR_ADCPRE_BY4 (0x1 << 16)
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#define ADC_CCR_ADCPRE_BY6 (0x2 << 16)
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#define ADC_CCR_ADCPRE_BY8 (0x3 << 16)
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/**@}*/
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#define ADC_CCR_ADCPRE_MASK (0x3 << 16)
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#define ADC_CCR_ADCPRE_SHIFT 16
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/* DMA: Direct memory access mode for multi ADC mode. */
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/****************************************************************************/
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/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode
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@ingroup adc_defines
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@{*/
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#define ADC_CCR_DMA_DISABLE (0x0 << 14)
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#define ADC_CCR_DMA_MODE_1 (0x1 << 14)
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#define ADC_CCR_DMA_MODE_2 (0x2 << 14)
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#define ADC_CCR_DMA_MODE_3 (0x3 << 14)
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/**@}*/
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#define ADC_CCR_DMA_MASK (0x3 << 14)
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#define ADC_CCR_DMA_SHIFT 14
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/* DDS: DMA disable selection (for multi-ADC mode). */
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#define ADC_CCR_DDS (1 << 13)
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/* Bit 12 reserved, must be kept at reset value */
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/* DELAY: Delay between 2 sampling phases. */
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/****************************************************************************/
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/** @defgroup adc_delay ADC Delay between 2 sampling phases
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@ingroup adc_defines
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@{*/
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#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8)
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#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8)
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#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8)
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#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8)
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#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8)
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#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8)
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#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8)
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#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8)
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#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8)
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#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8)
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#define ADC_CCR_DELAY_15ADCCLK (0xa << 8)
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#define ADC_CCR_DELAY_16ADCCLK (0xb << 8)
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#define ADC_CCR_DELAY_17ADCCLK (0xc << 8)
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#define ADC_CCR_DELAY_18ADCCLK (0xd << 8)
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#define ADC_CCR_DELAY_19ADCCLK (0xe << 8)
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#define ADC_CCR_DELAY_20ADCCLK (0xf << 8)
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/**@}*/
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#define ADC_CCR_DELAY_MASK (0xf << 8)
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#define ADC_CCR_DELAY_SHIFT 8
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/* Bit 7:5 reserved, must be kept at reset value */
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/* MULTI: Multi ADC mode selection. */
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/****************************************************************************/
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/** @defgroup adc_multi_mode ADC Multi mode selection
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@ingroup adc_defines
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@{*/
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/** All ADCs independent */
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#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0)
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/* Dual modes (ADC1 + ADC2) */
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/**
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* Dual modes (ADC1 + ADC2) Combined regular simultaneous +
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* injected simultaneous mode.
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*/
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#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0)
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/**
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* Dual modes (ADC1 + ADC2) Combined regular simultaneous +
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* alternate trigger mode.
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*/
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#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0)
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/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */
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#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0)
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/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */
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#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0)
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/** Dual modes (ADC1 + ADC2) Interleaved mode only. */
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#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0)
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/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */
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#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0)
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/* Triple modes (ADC1 + ADC2 + ADC3) */
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/**
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* Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous +
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* injected simultaneous mode.
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*/
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#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0)
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/**
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* Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous +
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* alternate trigger mode.
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*/
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#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0)
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/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */
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#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0)
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/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */
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#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0)
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/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */
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#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0)
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/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */
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#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0)
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/**@}*/
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#define ADC_CCR_MULTI_MASK (0x1f << 0)
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#define ADC_CCR_MULTI_SHIFT 0
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/* --- ADC_CDR values ------------------------------------------------------ */
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#define ADC_CDR_DATA2_MASK (0xffff << 16)
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#define ADC_CDR_DATA2_SHIFT 16
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#define ADC_CDR_DATA1_MASK (0xffff << 0)
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#define ADC_CDR_DATA1_SHIFT 0
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BEGIN_DECLS
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void adc_set_clk_prescale(uint32_t prescaler);
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void adc_set_multi_mode(uint32_t mode);
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void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
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uint32_t polarity);
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void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
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uint32_t polarity);
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void adc_set_resolution(uint32_t adc, uint32_t resolution);
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void adc_enable_overrun_interrupt(uint32_t adc);
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void adc_disable_overrun_interrupt(uint32_t adc);
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bool adc_get_overrun_flag(uint32_t adc);
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void adc_clear_overrun_flag(uint32_t adc);
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bool adc_awd(uint32_t adc);
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void adc_eoc_after_each(uint32_t adc);
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void adc_eoc_after_group(uint32_t adc);
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void adc_set_dma_continue(uint32_t adc);
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void adc_set_dma_terminate(uint32_t adc);
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void adc_enable_temperature_sensor(void);
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void adc_disable_temperature_sensor(void);
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void adc_enable_vbat_sensor(void);
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void adc_disable_vbat_sensor(void);
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END_DECLS
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#endif
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/** @cond */
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#endif
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/** @endcond */
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/**@}*/
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