499 lines
18 KiB
C
499 lines
18 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/** @file
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* @see EFM32TG_GPIO
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*/
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/** Definitions for the GPIO subsystem (General Purpose Input Output).
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*
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* This corresponds to the description in d0034_efm32tg_reference_manual.pdf
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* section 28.
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*
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* @ingroup EFM32TG
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* @defgroup EFM32TG_GPIO GPIO (General Purpose Input Output)
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* @{
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*/
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#ifndef LIBOPENCM3_EFM32_TINYGECKO_GPIO_H
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#define LIBOPENCM3_EFM32_TINYGECKO_GPIO_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/efm32/memorymap.h>
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/** Register definitions and register value definitions for the GPIO subsystem
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*
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* @defgroup EFM32TG_GPIO_regsandvals GPIO registers and values
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* @{
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*/
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/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 28.4
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*
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* The bulk of the registers defined here (like GPIO_PA_CTRL) will not be used
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* inside the convenience functions, but are provided for direct access.
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*
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* @todo This section could profit from bit-banding.
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*
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* @defgroup EFM32TG_GPIO_registers GPIO registers
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* @{
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*/
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#define GPIO_Px_CTRL(port) MMIO32(port + 0x000) /**< @see EFM32TG_GPIO_Px_CTRL_bits */
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#define GPIO_Px_MODEL(port) MMIO32(port + 0x004) /**< @see EFM32TG_GPIO_MODE_values */
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#define GPIO_Px_MODEH(port) MMIO32(port + 0x008) /**< @see EFM32TG_GPIO_MODE_values */
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#define GPIO_Px_DOUT(port) MMIO32(port + 0x00C) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_Px_DOUTSET(port) MMIO32(port + 0x010) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_Px_DOUTCLR(port) MMIO32(port + 0x014) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_Px_DOUTTGL(port) MMIO32(port + 0x018) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_Px_DIN(port) MMIO32(port + 0x01C) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_Px_PINLOCKN(port) MMIO32(port + 0x020) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_PA (GPIO_BASE + 0x000)
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#define GPIO_PA_CTRL GPIO_Px_CTRL(GPIO_PA)
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#define GPIO_PA_MODEL GPIO_Px_MODEL(GPIO_PA)
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#define GPIO_PA_MODEH GPIO_Px_MODEH(GPIO_PA)
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#define GPIO_PA_DOUT GPIO_Px_DOUT(GPIO_PA)
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#define GPIO_PA_DOUTSET GPIO_Px_DOUTSET(GPIO_PA)
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#define GPIO_PA_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PA)
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#define GPIO_PA_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PA)
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#define GPIO_PA_DIN GPIO_Px_DIN(GPIO_PA)
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#define GPIO_PA_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PA)
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#define GPIO_PB (GPIO_BASE + 0x024)
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#define GPIO_PB_CTRL GPIO_Px_CTRL(GPIO_PB)
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#define GPIO_PB_MODEL GPIO_Px_MODEL(GPIO_PB)
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#define GPIO_PB_MODEH GPIO_Px_MODEH(GPIO_PB)
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#define GPIO_PB_DOUT GPIO_Px_DOUT(GPIO_PB)
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#define GPIO_PB_DOUTSET GPIO_Px_DOUTSET(GPIO_PB)
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#define GPIO_PB_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PB)
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#define GPIO_PB_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PB)
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#define GPIO_PB_DIN GPIO_Px_DIN(GPIO_PB)
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#define GPIO_PB_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PB)
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#define GPIO_PC (GPIO_BASE + 0x048)
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#define GPIO_PC_CTRL GPIO_Px_CTRL(GPIO_PC)
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#define GPIO_PC_MODEL GPIO_Px_MODEL(GPIO_PC)
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#define GPIO_PC_MODEH GPIO_Px_MODEH(GPIO_PC)
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#define GPIO_PC_DOUT GPIO_Px_DOUT(GPIO_PC)
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#define GPIO_PC_DOUTSET GPIO_Px_DOUTSET(GPIO_PC)
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#define GPIO_PC_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PC)
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#define GPIO_PC_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PC)
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#define GPIO_PC_DIN GPIO_Px_DIN(GPIO_PC)
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#define GPIO_PC_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PC)
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#define GPIO_PD (GPIO_BASE + 0x06C)
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#define GPIO_PD_CTRL GPIO_Px_CTRL(GPIO_PD)
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#define GPIO_PD_MODEL GPIO_Px_MODEL(GPIO_PD)
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#define GPIO_PD_MODEH GPIO_Px_MODEH(GPIO_PD)
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#define GPIO_PD_DOUT GPIO_Px_DOUT(GPIO_PD)
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#define GPIO_PD_DOUTSET GPIO_Px_DOUTSET(GPIO_PD)
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#define GPIO_PD_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PD)
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#define GPIO_PD_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PD)
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#define GPIO_PD_DIN GPIO_Px_DIN(GPIO_PD)
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#define GPIO_PD_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PD)
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#define GPIO_PE (GPIO_BASE + 0x090)
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#define GPIO_PE_CTRL GPIO_Px_CTRL(GPIO_PE)
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#define GPIO_PE_MODEL GPIO_Px_MODEL(GPIO_PE)
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#define GPIO_PE_MODEH GPIO_Px_MODEH(GPIO_PE)
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#define GPIO_PE_DOUT GPIO_Px_DOUT(GPIO_PE)
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#define GPIO_PE_DOUTSET GPIO_Px_DOUTSET(GPIO_PE)
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#define GPIO_PE_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PE)
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#define GPIO_PE_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PE)
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#define GPIO_PE_DIN GPIO_Px_DIN(GPIO_PE)
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#define GPIO_PE_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PE)
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#define GPIO_PF (GPIO_BASE + 0x0B4)
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#define GPIO_PF_CTRL GPIO_Px_CTRL(GPIO_PF)
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#define GPIO_PF_MODEL GPIO_Px_MODEL(GPIO_PF)
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#define GPIO_PF_MODEH GPIO_Px_MODEH(GPIO_PF)
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#define GPIO_PF_DOUT GPIO_Px_DOUT(GPIO_PF)
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#define GPIO_PF_DOUTSET GPIO_Px_DOUTSET(GPIO_PF)
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#define GPIO_PF_DOUTCLR GPIO_Px_DOUTCLR(GPIO_PF)
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#define GPIO_PF_DOUTTGL GPIO_Px_DOUTTGL(GPIO_PF)
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#define GPIO_PF_DIN GPIO_Px_DIN(GPIO_PF)
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#define GPIO_PF_PINLOCKN GPIO_Px_PINLOCKN(GPIO_PF)
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#define GPIO_EXTIPSELL MMIO32(GPIO_BASE + 0x100) /**< @see EFM32TG_GPIO_EXTIP_values */
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#define GPIO_EXTIPSELH MMIO32(GPIO_BASE + 0x104) /**< @see EFM32TG_GPIO_EXTIP_values */
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#define GPIO_EXTIRISE MMIO32(GPIO_BASE + 0x108) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_EXTIFALL MMIO32(GPIO_BASE + 0x10C) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_IEN MMIO32(GPIO_BASE + 0x110) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_IF MMIO32(GPIO_BASE + 0x114) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_IFS MMIO32(GPIO_BASE + 0x118) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_IFC MMIO32(GPIO_BASE + 0x11C) /**< @see EFM32TG_GPIO_pinnumberbits */
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#define GPIO_ROUTE MMIO32(GPIO_BASE + 0x120) /**< @see EFM32TG_GPIO_ROUTE_bits */
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#define GPIO_INSENSE MMIO32(GPIO_BASE + 0x124) /**< @see EFM32TG_GPIO_INSENSE_bits */
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#define GPIO_LOCK MMIO32(GPIO_BASE + 0x128) /**< @see EFM32TG_GPIO_LOCK_values */
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#define GPIO_CTRL MMIO32(GPIO_BASE + 0x12C) /**< @see EFM32TG_GPIO_CTRL_bits */
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#define GPIO_CMD MMIO32(GPIO_BASE + 0x130) /**< @see EFM32TG_GPIO_CMD_bits */
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#define GPIO_EM4WUEN MMIO32(GPIO_BASE + 0x134) /**< @see EFM32TG_GPIO_EM4WUEN_bits */
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#define GPIO_EM4WUPOL MMIO32(GPIO_BASE + 0x138) /**< @see EFM32TG_GPIO_EM4WUPOL_bits */
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#define GPIO_EM4WUCAUSE MMIO32(GPIO_BASE + 0x13C) /**< @see EFM32TG_GPIO_EM4WUCAUSE_bits */
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/** @} */
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/** Pin number bits
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*
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* Provided for convenience. They can be used on the GPIO_Px_DOUT,
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* GPIO_Px_DOUTSET, GPIO_Px_DOUTCLR, GPIO_Px_DOUTTGL, GPIO_Px_DIN,
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* GPIO_Px_PINLOCKN, GPIO_Px_EXTIRISE, GPIO_Px_EXTIFALL, GPIO_IEN, GPIO_IF,
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* GPIO_IFS, and GPIO_IFC registers.
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*
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* @defgroup EFM32TG_GPIO_pinnumberbits GPIO pin number bits
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* @{
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*/
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#define GPIO0 (1 << 0)
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#define GPIO1 (1 << 1)
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#define GPIO2 (1 << 2)
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#define GPIO3 (1 << 3)
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#define GPIO4 (1 << 4)
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#define GPIO5 (1 << 5)
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#define GPIO6 (1 << 6)
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#define GPIO7 (1 << 7)
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#define GPIO8 (1 << 8)
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#define GPIO9 (1 << 9)
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#define GPIO10 (1 << 10)
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#define GPIO11 (1 << 11)
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#define GPIO12 (1 << 12)
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#define GPIO13 (1 << 13)
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#define GPIO14 (1 << 14)
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#define GPIO15 (1 << 15)
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#define GPIO_ALL 0xffff
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/** @} */
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/** Bit states for the GPIO_Px_CTRL register
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*
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* They are named as in d0034_efm32tg_reference_manual.pdf's section
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* 28.5.1.
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*
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* @defgroup EFM32TG_GPIO_Px_CTRL_bits GPIO Px CTRL bits
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* @{
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*/
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#define GPIO_CTRL_DRIVEMODE_STANDARD 0 /**< 6mA drive current */
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#define GPIO_CTRL_DRIVEMODE_LOWEST 1 /**< 0.5mA drive current */
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#define GPIO_CTRL_DRIVEMODE_HIGH 2 /**< 20mA drive current */
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#define GPIO_CTRL_DRIVEMODE_LOW 3 /**< 2mA drive current */
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/** @} */
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/** These are the modes defined for the MODEx fields in the GPIO_Px_MODEL and
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* GPIO_Px_MODEH registers.
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*
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* These bit state definitions are not localized, meaning that they have to be
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* bitshifted by multiples of 4 to configure other pins than 0; configurations
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* for pins 0 to 7 go to GPIO_Px_MODEL (shifted by 4*pin), configurations for
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* pins 8 to 15 go to GPIO_Px_MODEH (shifted by 4*(pin-8)).
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*
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* For example, to set the mode for the 3rd pin of port A to pushpull, set
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* `GPIO_PA_MODEL = GPIO_MODE_PUSHPULL << (3*4);`.
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*
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* @todo Update the example as soon as there are convenience functions to do
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* this properly.
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*
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* They are named as in d0034_efm32tg_reference_manual.pdf's sections
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* 28.5.2/28.5.3. For explanations of what they really do, rather see section
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* 28.3.1.
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*
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* @defgroup EFM32TG_GPIO_MODE_values GPIO MODE values
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* @{
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*/
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#define GPIO_MODE_DISABLED 0
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#define GPIO_MODE_INPUT 1
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#define GPIO_MODE_INPUTPULL 2
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#define GPIO_MODE_INPUTPULLFILTER 3
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#define GPIO_MODE_PUSHPULL 4
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#define GPIO_MODE_PUSHPULLDRIVE 5
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#define GPIO_MODE_WIREDOR 6
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#define GPIO_MODE_WIREDORPULLDOWN 7
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#define GPIO_MODE_WIREDAND 8
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#define GPIO_MODE_WIREDANDFILTER 9
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#define GPIO_MODE_WIREDANDPULLUP 10
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#define GPIO_MODE_WIREDANDPULLUPFILTER 11
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#define GPIO_MODE_WIREDANDDRIVE 12
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#define GPIO_MODE_WIREDANDDRIVEFILTER 13
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#define GPIO_MODE_WIREDANDDRIVEPULLUP 14
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#define GPIO_MODE_WIREDANDDRIVEPULLUPFILTER 15
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#define GPIO_MODE_MASK 0x0f
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/** @} */
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/** These are the modes defined for the EXTIPSELx fields in the GPIO_EXTIPSELL
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* and GPIO_EXTIPSELH registers.
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*
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* These bit state definitions are not localized, meaning that they have to be
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* bitshifted by multiples of 4 to configure other pins than 0; configurations
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* for pins 0 to 7 go to GPIO_EXTIPSELL (shifted by 4*pin), configurations for
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* pins 8 to 15 go to GPIO_EXTIPSELH (shifted by 4*(pin-8)).
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*
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* They are named as in d0034_efm32tg_reference_manual.pdf's sections
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* 28.5.10/28.5.11. For explanations of what they do, rather see section
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* 28.3.5.
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*
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* @defgroup EFM32TG_GPIO_EXTIP_values GPIO EXTIPSEL values
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* @{
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*/
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#define GPIO_EXTIPSEL_PORTA 0 /**< Port A pin x selected for external interrupt x */
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#define GPIO_EXTIPSEL_PORTB 1 /**< Port B pin x selected for external interrupt x */
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#define GPIO_EXTIPSEL_PORTC 2 /**< Port C pin x selected for external interrupt x */
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#define GPIO_EXTIPSEL_PORTD 3 /**< Port D pin x selected for external interrupt x */
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#define GPIO_EXTIPSEL_PORTE 4 /**< Port E pin x selected for external interrupt x */
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#define GPIO_EXTIPSEL_PORTF 5 /**< Port F pin x selected for external interrupt x */
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/** @} */
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/** Bit states for the GPIO_ROUTE register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.18 for definitions, and
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* 28.3.4.1 for explanations.
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*
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* @defgroup EFM32TG_GPIO_ROUTE_bits GPIO ROUTE bits
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* @{
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*/
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#define GPIO_ROUTE_SWLOCATION_MASK (0x03<<8)
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#define GPIO_ROUTE_SWLOCATION_LOC0 (0<<8) /**< Route SW pins to location 0 (see chip data sheet for exact pins */
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#define GPIO_ROUTE_SWLOCATION_LOC1 (1<<8) /**< Route SW pins to location 1 (see chip data sheet for exact pins */
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#define GPIO_ROUTE_SWLOCATION_LOC2 (2<<8) /**< Route SW pins to location 2 (see chip data sheet for exact pins */
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#define GPIO_ROUTE_SWLOCATION_LOC3 (3<<8) /**< Route SW pins to location 3 (see chip data sheet for exact pins */
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#define GPIO_ROUTE_SWOPEN (1<<2) /**< Serial Wire Viewer Output pin enabled */
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#define GPIO_ROUTE_SWDIOPEN (1<<1) /**< Serial Wire Data pin enabled */
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#define GPIO_ROUTE_SWCLKPEN (1<<0) /**< Serial Wire Clock pin enabled */
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/** @} */
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/** Bit states for the GPIO_INSENSE register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.19 for definitions, and
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* 28.3.7 for details.
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*
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* @defgroup EFM32TG_GPIO_INSENSE_bits GPIO INSENSE bits
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* @{
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*/
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#define GPIO_INSENSE_PRS (1<<1) /**< Input sensing for PRS enabled */
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#define GPIO_INSENSE_INT (1<<0) /**< Input sensing for interrupts enabled */
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/** @} */
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/** Values for the GPIO_LOCK register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.20 for definitions, and
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* 28.3.1.1 for explanations.
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*
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* @defgroup EFM32TG_GPIO_LOCK_values GPIO LOCK bits
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* @{
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*/
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#define GPIO_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */
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#define GPIO_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */
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#define GPIO_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock down GPIO */
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#define GPIO_LOCK_SET_UNLOCKED 0xa543 /**< Write this to the LOCK register to unlock the GPIO */
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/** @} */
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/** Bit states for the GPIO_CTRL register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.21 for definitions, and
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* 28.3.4 for explanations.
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*
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* @defgroup EFM32TG_GPIO_CTRL_bits GPIO CTRL bits
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* @{
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*/
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#define GPIO_CTRL_EM4RET (1<<0) /**< Retention of states in EM4 */
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/** @} */
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/** Bit states for the GPIO_CMD register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.22 for definitions and
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* figure 28.5 in case you wonder if that register is mentioned anywhere else
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* at all.
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*
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* @defgroup EFM32TG_GPIO_CMD_bits GPIO CMD bits
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* @{
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*/
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#define GPIO_CMD_EM4WUCLR (1<<0) /**< Write this flag to clear EM4 wakeup requests */
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/** @} */
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/** Bit states for the GPIO_EM4WUEN register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.23 for definitions, and
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* 28.3.2 for explanations.
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*
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* @defgroup EFM32TG_GPIO_EM4WUEN_bits GPIO EM4WUEN bits
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* @{
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*/
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#define GPIO_EM4WUEN_A0 0x01 /**< Wake up from EM4 on A0 activity */
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#define GPIO_EM4WUEN_A6 0x02 /**< Wake up from EM4 on A6 activity */
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#define GPIO_EM4WUEN_C9 0x04 /**< Wake up from EM4 on C9 activity */
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#define GPIO_EM4WUEN_F1 0x08 /**< Wake up from EM4 on F1 activity */
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#define GPIO_EM4WUEN_F3 0x10 /**< Wake up from EM4 on F3 activity */
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#define GPIO_EM4WUEN_E13 0x20 /**< Wake up from EM4 on E13 activity */
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/** @} */
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/** Bit states for the GPIO_EM4WUPOL register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.24 for definitions, and
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* 28.3.2 for explanations.
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*
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* @defgroup EFM32TG_GPIO_EM4WUPOL_bits GPIO EM4WUPOL bits
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* @{
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*/
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#define GPIO_EM4WUPOL_A0 0x01 /**< High wake up from EM4 on A0 */
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#define GPIO_EM4WUPOL_A6 0x02 /**< High wake up from EM4 on A6 */
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#define GPIO_EM4WUPOL_C9 0x04 /**< High wake up from EM4 on C9 */
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#define GPIO_EM4WUPOL_F1 0x08 /**< High wake up from EM4 on F1 */
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#define GPIO_EM4WUPOL_F3 0x10 /**< High wake up from EM4 on F3 */
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#define GPIO_EM4WUPOL_E13 0x20 /**< High wake up from EM4 on E13 */
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/** @} */
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/** Bit states for the GPIO_EM4WUCAUSE register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.25 for definitions, and
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* 28.3.2 for explanations.
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*
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* @defgroup EFM32TG_GPIO_EM4WUCAUSE_bits GPIO EM4WUCAUSE bits
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* @{
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*/
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#define GPIO_EM4WUCAUSE_A0 0x01 /**< Woke up from EM4 on A0 */
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#define GPIO_EM4WUCAUSE_A6 0x02 /**< Woke up from EM4 on A6 */
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#define GPIO_EM4WUCAUSE_C9 0x04 /**< Woke up from EM4 on C9 */
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#define GPIO_EM4WUCAUSE_F1 0x08 /**< Woke up from EM4 on F1 */
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#define GPIO_EM4WUCAUSE_F3 0x10 /**< Woke up from EM4 on F3 */
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#define GPIO_EM4WUCAUSE_E13 0x20 /**< Woke up from EM4 on E13 */
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/** @} */
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/** @} */
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/** GPIO convenience functions
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*
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* These functions try to be close to the STM32 F1 utility functions where
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* possible.
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*
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* The functions intentionally don't cover all the possible read- and write
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* operations to the GPIO registers. For example, reading the configured output
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* strength for a port is rarely required.
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*
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* Many convenience functions are static to allow inlining by the compiler.
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*
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* @todo Implement all the non-trivial but useful convenience functions.
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*
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* @defgroup EFM32TG_GPIO_convenience GPIO convenience functions
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* @{
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*/
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/** Set a whole GPIO port's out data to a particular value
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*
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* \param gpioport Address of a GPIO port to use (eg GPIO_PA)
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* \param gpios Bit pattern the output of the port will be configured to (eg GPIO6|GPIO3 to switch pins 6 and 3 to high and all the others to low)
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*/
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static void gpio_port_write(u32 gpioport, u16 data)
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{
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GPIO_Px_DOUT(gpioport) = data;
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}
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/** Set some bits in a GPIO port's out data
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*
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* \param gpioport Address of a GPIO port to use (eg GPIO_PA)
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* \param gpios GPIO pin(s) to be set to 1 (eg GPIO6|GPIO3 to switch pins 6 and 3 to high and leave all the others in their previous state)
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*/
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static void gpio_set(u32 gpioport, u16 gpios)
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{
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GPIO_Px_DOUTSET(gpioport) = gpios;
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}
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/** Clear some bits in a GPIO port's out data
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*
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* \param gpioport Address of a GPIO port to use (eg GPIO_PA)
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* \param gpios GPIO pin(s) to be set to 0 (eg GPIO6|GPIO3 to switch pins 6 and 3 to low and leave all the others in their previous state)
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*/
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static void gpio_clear(u32 gpioport, u16 gpios)
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{
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GPIO_Px_DOUTCLR(gpioport) = gpios;
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}
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/** Toggle some bits in a GPIO port's out data
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*
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* \param gpioport Address of a GPIO port to use (eg GPIO_PA)
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* \param gpios GPIO pin(s) that will be toggled (eg GPIO6|GPIO3 to toggle the output directions of pins 6 and 3 and leave all the others in their previous state)
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*/
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static void gpio_toggle(u32 gpioport, u16 gpios)
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{
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GPIO_Px_DOUTTGL(gpioport) = gpios;
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}
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/** Read input bits from a GPIO's port in data
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*
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* \param gpioport Address of a GPIO port to use (eg GPIO_PA)
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* \returns Current value of the in register of the given port
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*/
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static u16 gpio_port_read(u32 gpioport)
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{
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return GPIO_Px_DIN(gpioport);
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}
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/** Read input bits from a GPIO's port in data
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*
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* \param gpioport Address of a GPIO port to use (eg GPIO_PA)
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* \param gpios Bits that will be read (eg GPIO6|GPIO3 to read pins 6 and 3)
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* \returns Bit pattern that contains 1 in all pin positions that currently read as high (eg GPIO6 if port A's 6th pin is currently high and the 3rd pin is low)
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*/
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static u16 gpio_get(u32 gpioport, u16 gpios)
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{
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return gpio_port_read(gpioport) & gpios;
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}
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/** Configure a particular pin configuration on one or more pins
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*
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* This function is not atomic. It has to be made sure that it is not
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* interrupted by other code that modifies the port's configuration.
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*
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* \param gpioport Address of a GPIO port to use (eg GPIO_PA)
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* \param mode Pin configuration mode to set (eg GPIO_MODE_INPUT)
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* \param gpios Pins to configure (eg GPIO6|GPIO3 to set the mode on pins 6 and 3)
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*/
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void gpio_set_mode(u32 gpioport, u8 mode, u16 gpios);
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/** Configure the alternate drive strength for a port
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*
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* \param gpioport Address of a GPIO port to use (eg GPIO_PA)
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* \param strength Alternate drive strength to configure for the port (eg GPIO_CTRL_DRIVEMODE_HIGH)
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*/
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static void gpio_set_strength(u32 gpioport, u8 strength)
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{
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GPIO_Px_CTRL(gpioport) = strength;
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}
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/** @} */
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/** @} */
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#endif
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