152 lines
5.4 KiB
C
152 lines
5.4 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_NVIC_H
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#define LPC43XX_NVIC_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/cm3/memorymap.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- NVIC Registers ------------------------------------------------------ */
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/* ISER: Interrupt Set Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
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/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
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/* ICER: Interrupt Clear Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
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/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
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/* ISPR: Interrupt Set Pending Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
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/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
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/* ICPR: Interrupt Clear Pending Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
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/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
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/* IABR: Interrupt Active Bit Register */
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/* Note: 8 32bit Registers */
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#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
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/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
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/* IPR: Interrupt Priority Registers */
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/* Note: 240 8bit Registers */
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#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
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/* STIR: Software Trigger Interrupt Register */
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#define NVIC_STIR MMIO32(STIR_BASE)
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/* --- IRQ channel numbers-------------------------------------------------- */
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/* Cortex M4 System Interrupts */
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#define NVIC_NMI_IRQ -14
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#define NVIC_HARD_FAULT_IRQ -13
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#define NVIC_MEM_MANAGE_IRQ -12
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#define NVIC_BUS_FAULT_IRQ -11
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#define NVIC_USAGE_FAULT_IRQ -10
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/* irq numbers -6 to -9 are reserved */
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#define NVIC_SV_CALL_IRQ -5
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#define DEBUG_MONITOR_IRQ -4
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/* irq number -3 reserved */
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#define NVIC_PENDSV_IRQ -2
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#define NVIC_SYSTICK_IRQ -1
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/* LPC43xx M4 specific user interrupts */
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#define NVIC_M4_DAC_IRQ 0
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#define NVIC_M4_M0CORE_IRQ 1
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#define NVIC_M4_DMA_IRQ 2
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#define NVIC_M4_ETHERNET_IRQ 5
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#define NVIC_M4_SDIO_IRQ 6
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#define NVIC_M4_LCD_IRQ 7
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#define NVIC_M4_USB0_IRQ 8
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#define NVIC_M4_USB1_IRQ 9
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#define NVIC_M4_SCT_IRQ 10
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#define NVIC_M4_RITIMER_IRQ 11
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#define NVIC_M4_TIMER0_IRQ 12
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#define NVIC_M4_TIMER1_IRQ 13
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#define NVIC_M4_TIMER2_IRQ 14
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#define NVIC_M4_TIMER3_IRQ 15
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#define NVIC_M4_MCPWM_IRQ 16
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#define NVIC_M4_ADC0_IRQ 17
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#define NVIC_M4_I2C0_IRQ 18
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#define NVIC_M4_I2C1_IRQ 19
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#define NVIC_M4_SPI_IRQ 20
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#define NVIC_M4_ADC1_IRQ 21
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#define NVIC_M4_SSP0_IRQ 22
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#define NVIC_M4_SSP1_IRQ 23
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#define NVIC_M4_USART0_IRQ 24
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#define NVIC_M4_UART1_IRQ 25
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#define NVIC_M4_USART2_IRQ 26
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#define NVIC_M4_USART3_IRQ 27
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#define NVIC_M4_I2S0_IRQ 28
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#define NVIC_M4_I2S1_IRQ 29
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#define NVIC_M4_SPIFI_IRQ 30
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#define NVIC_M4_SGPIO_IRQ 31
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#define NVIC_M4_PIN_INT0_IRQ 32
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#define NVIC_M4_PIN_INT1_IRQ 33
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#define NVIC_M4_PIN_INT2_IRQ 34
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#define NVIC_M4_PIN_INT3_IRQ 35
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#define NVIC_M4_PIN_INT4_IRQ 36
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#define NVIC_M4_PIN_INT5_IRQ 37
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#define NVIC_M4_PIN_INT6_IRQ 38
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#define NVIC_M4_PIN_INT7_IRQ 39
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#define NVIC_M4_GINT0_IRQ 40
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#define NVIC_M4_GINT1_IRQ 41
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#define NVIC_M4_EVENTROUTER_IRQ 42
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#define NVIC_M4_C_CAN1_IRQ 43
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#define NVIC_M4_ATIMER_IRQ 46
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#define NVIC_M4_RTC_IRQ 47
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#define NVIC_M4_WWDT_IRQ 49
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#define NVIC_M4_C_CAN0_IRQ 51
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#define NVIC_M4_QEI_IRQ 52
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/* LPC43xx M0 specific user interrupts */
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//TODO
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/* --- NVIC functions ------------------------------------------------------ */
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BEGIN_DECLS
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void nvic_enable_irq(u8 irqn);
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void nvic_disable_irq(u8 irqn);
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u8 nvic_get_pending_irq(u8 irqn);
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void nvic_set_pending_irq(u8 irqn);
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void nvic_clear_pending_irq(u8 irqn);
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u8 nvic_get_active_irq(u8 irqn);
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u8 nvic_get_irq_enabled(u8 irqn);
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void nvic_set_priority(u8 irqn, u8 priority);
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void nvic_generate_software_interrupt(u8 irqn);
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END_DECLS
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#endif
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