161 lines
5.1 KiB
C
161 lines
5.1 KiB
C
/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENSTM32_SPI_H
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#define LIBOPENSTM32_SPI_H
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#include <libopenstm32.h>
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/* Registers can be accessed as 16bit or 32bit values. */
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/* --- Convenience macros -------------------------------------------------- */
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#define SPI1 SPI1_BASE
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#define SPI2 SPI2_I2S_BASE
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#define SPI3 SPI3_I2S_BASE
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/* --- SPI registers ------------------------------------------------------- */
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/* Control register 1 (SPIx_CR1) */
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#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00)
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#define SPI1_CR1 SPI_CR1(SPI1_BASE)
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#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE)
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#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE)
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/* Control register 2 (SPIx_CR2) */
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#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04)
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#define SPI1_CR2 SPI_CR2(SPI1_BASE)
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#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE)
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#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE)
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/* Status register (SPIx_SR) */
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#define SPI_SR(spi_base) MMIO32(spi_base + 0x08)
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#define SPI1_SR SPI_SR(SPI1_BASE)
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#define SPI2_SR SPI_SR(SPI2_I2S_BASE)
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#define SPI3_SR SPI_SR(SPI3_I2S_BASE)
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/* Data register (SPIx_DR) */
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#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c)
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#define SPI1_DR SPI_DR(SPI1_BASE)
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#define SPI2_DR SPI_DR(SPI2_I2S_BASE)
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#define SPI3_DR SPI_DR(SPI3_I2S_BASE)
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/* CRC polynomial register (SPIx_CRCPR) */
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/* Note: Not used in I2S mode. */
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#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10)
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#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE)
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#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE)
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#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE)
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/* RX CRC register (SPIx_RXCRCR) */
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/* Note: Not used in I2S mode. */
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#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14)
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#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)
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#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE)
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#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE)
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/* TX CRC register (SPIx_RXCRCR) */
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/* Note: Not used in I2S mode. */
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#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18)
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#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)
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#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE)
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#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE)
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/* I2S configuration register (SPIx_I2SCFGR) */
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#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c)
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#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)
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#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE)
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#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE)
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/* I2S prescaler register (SPIx_I2SPR) */
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#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20)
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#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE)
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#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE)
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#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE)
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/* --- SPI_CR1 values ------------------------------------------------------ */
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/* Note: None of the CR1 bits are used in I2S mode. */
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/* BIDIMODE: Bidirectional data mode enable */
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#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15)
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#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15)
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/* BIDIOE: Output enable in bidirectional mode */
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#define SPI_CR1_BIDIOE (1 << 14)
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/* CRCEN: Hardware CRC calculation enable */
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#define SPI_CR1_CRCEN (1 << 13)
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/* CRCNEXT: Transmit CRC next */
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#define SPI_CR1_CRCNEXT (1 << 12)
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/* DFF: Data frame format */
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#define SPI_CR1_DFF_8BIT (0 << 11)
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#define SPI_CR1_DFF_16BIT (1 << 11)
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/* RXONLY: Receive only */
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#define SPI_CR1_RXONLY (1 << 10)
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/* SSM: Software slave management */
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#define SPI_CR1_SSM (1 << 9)
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/* SSI: Internal slave select */
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#define SPI_CR1_SSI (1 << 8)
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/* LSBFIRST: Frame format */
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#define SPI_CR1_MSBFIRST (0 << 7)
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#define SPI_CR1_LSBFIRST (1 << 7)
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/* SPE: SPI enable */
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#define SPI_CR1_SPE (1 << 6)
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/* BR[2:0]: Baud rate control */
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
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/* MSTR: Master selection */
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#define SPI_CR1_MSTR (1 << 2)
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/* CPOL: Clock polarity */
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#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
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#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
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/* CPHA: Clock phase */
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#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
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#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
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/* --- Function prototypes ------------------------------------------------- */
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int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
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void spi_enable(u32 spi);
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void spi_disable(u32 spi);
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void spi_write(u32 spi, u16 data);
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u16 spi_read(u32 spi);
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/* TODO */
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#endif
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