551 lines
16 KiB
C
551 lines
16 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Felix Held <felix-libopencm3@felixheld.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_SMC_H
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#define LIBOPENCM3_SMC_H
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#include <libopencm3/sam/memorymap.h>
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/* Chip Select Defines */
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#define SMC_CS_0 0
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#define SMC_CS_1 1
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#define SMC_CS_2 2
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#define SMC_CS_3 3
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/* --- Static Memory Controller (SMC) registers ---------------------------- */
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/* NFC Configuration Register */
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#define SMC_CFG MMIO32(SMC_BASE + 0x00)
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/* NFC Control Register */
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#define SMC_CTRL MMIO32(SMC_BASE + 0x04)
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/* NFC Status Register */
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#define SMC_SR MMIO32(SMC_BASE + 0x08)
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/* NFC Interrupt Enable Register */
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#define SMC_IER MMIO32(SMC_BASE + 0x0C)
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/* NFC Interrupt Disable Register */
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#define SMC_IDR MMIO32(SMC_BASE + 0x10)
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/* Interrupt Mask Register */
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#define SMC_IMR MMIO32(SMC_BASE + 0x14)
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/* NFC Address Cycle Zero Register */
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#define SMC_ADDR MMIO32(SMC_BASE + 0x18)
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/* Bank Address Register */
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#define SMC_BANK MMIO32(SMC_BASE + 0x1C)
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/* ECC Control Register */
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#define SMC_ECC_CTRL MMIO32(SMC_BASE + 0x20)
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/* ECC Mode Register */
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#define SMC_ECC_MD MMIO32(SMC_BASE + 0x24)
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/* ECC Status 1 Register */
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#define SMC_ECC_SR1 MMIO32(SMC_BASE + 0x28)
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/* ECC Parity 0 Register */
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#define SMC_ECC_PR0 MMIO32(SMC_BASE + 0x2C)
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/* ECC parity 1 Register */
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#define SMC_ECC_PR1 MMIO32(SMC_BASE + 0x30)
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/* ECC status 2 Register */
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#define SMC_ECC_SR2 MMIO32(SMC_BASE + 0x34)
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/* ECC parity 2 Register */
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#define SMC_ECC_PR2 MMIO32(SMC_BASE + 0x38)
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/* ECC parity 3 Register */
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#define SMC_ECC_PR3 MMIO32(SMC_BASE + 0x3C)
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/* ECC parity 4 Register */
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#define SMC_ECC_PR4 MMIO32(SMC_BASE + 0x40)
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/* ECC parity 5 Register */
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#define SMC_ECC_PR5 MMIO32(SMC_BASE + 0x44)
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/* ECC parity 6 Register */
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#define SMC_ECC_PR6 MMIO32(SMC_BASE + 0x48)
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/* ECC parity 7 Register */
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#define SMC_ECC_PR7 MMIO32(SMC_BASE + 0x4C)
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/* ECC parity 8 Register */
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#define SMC_ECC_PR8 MMIO32(SMC_BASE + 0x50)
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/* ECC parity 9 Register */
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#define SMC_ECC_PR9 MMIO32(SMC_BASE + 0x54)
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/* ECC parity 10 Register */
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#define SMC_ECC_PR10 MMIO32(SMC_BASE + 0x58)
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/* ECC parity 11 Register */
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#define SMC_ECC_PR11 MMIO32(SMC_BASE + 0x5C)
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/* ECC parity 12 Register */
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#define SMC_ECC_PR12 MMIO32(SMC_BASE + 0x60)
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/* ECC parity 13 Register */
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#define SMC_ECC_PR13 MMIO32(SMC_BASE + 0x64)
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/* ECC parity 14 Register */
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#define SMC_ECC_PR14 MMIO32(SMC_BASE + 0x68)
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/* ECC parity 15 Register */
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#define SMC_ECC_PR15 MMIO32(SMC_BASE + 0x6C)
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/* Setup Register */
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#define SMC_SETUP(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) + 0x70)
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/* Pulse Register */
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#define SMC_PULSE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) + 0x74)
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/* Cycle Register */
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#define SMC_CYCLE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) + 0x78)
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/* Timings Register */
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#define SMC_TIMINGS(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) + 0x7C)
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/* Mode Register */
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#define SMC_MODE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) + 0x80)
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/* Off Chip Memory Scrambling Mode Register */
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#define SMC_OCMS MMIO32(SMC_BASE + 0x110)
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/* Off Chip Memory Scrambling KEY1 Register */
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#define SMC_KEY1 MMIO32(SMC_BASE + 0x114)
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/* Off Chip Memory Scrambling KEY2 Register */
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#define SMC_KEY2 MMIO32(SMC_BASE + 0x118)
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/* Write Protection Control Register */
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#define SMC_WPCR MMIO32(SMC_BASE + 0x1E4)
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/* Write Protect Status Register */
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#define SMC_WPSR MMIO32(SMC_BASE + 0x1E8)
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/* --- Register contents --------------------------------------------------- */
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/* --- SMC NFC Configuration Register (SMC_CFG) ---------------------------- */
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/* Data Timeout Multiplier */
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#define SMC_CFG_DTOMUL_SHIFT 20
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#define SMC_CFG_DTOMUL_MASK (0x07 << SMC_DTOMUL_SHIFT)
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/* Data Timeout Multiplier Values */
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#define SMC_CFG_DTOMUL_X1 (0x00 << SMC_DTOMUL_SHIFT)
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#define SMC_CFG_DTOMUL_X16 (0x01 << SMC_DTOMUL_SHIFT)
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#define SMC_CFG_DTOMUL_X128 (0x02 << SMC_DTOMUL_SHIFT)
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#define SMC_CFG_DTOMUL_X256 (0x03 << SMC_DTOMUL_SHIFT)
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#define SMC_CFG_DTOMUL_X1024 (0x04 << SMC_DTOMUL_SHIFT)
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#define SMC_CFG_DTOMUL_X4096 (0x05 << SMC_DTOMUL_SHIFT)
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#define SMC_CFG_DTOMUL_X65536 (0x06 << SMC_DTOMUL_SHIFT)
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#define SMC_CFG_DTOMUL_X1048576 (0x07 << SMC_DTOMUL_SHIFT)
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/* Data Timeout Cycle Number */
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#define SMC_CFG_DTOCYC_SHIFT 16
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#define SMC_CFG_DTOCYC_MASK (0x0F << SMC_DTOCYC_SHIFT)
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/* Ready/Busy Signal Edge Detection */
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#define SMC_CFG_RBEDGE (1 << 13)
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/* Rising/Falling Edge Detection Control */
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#define SMC_CFG_EDGECTRL (1 << 12)
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/* Read Spare Area */
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#define SMC_CFG_RSPARE (1 << 9)
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/* Write Spare Area */
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#define SMC_CFG_WSPARE (1 << 8)
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/* NAND Flash Page Size */
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#define SMC_CFG_PAGESIZE_SHIFT 0
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#define SMC_CFG_PAGESIZE_MASK (0x03 << SMC_CFG_PAGESIZE_SHIFT)
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/* NAND Flash Page Size Values */
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#define SMC_CFG_PAGESIZE_PS512_16 (0x00 << SMC_CFG_PAGESIZE_SHIFT)
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#define SMC_CFG_PAGESIZE_PS1024_32 (0x01 << SMC_CFG_PAGESIZE_SHIFT)
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#define SMC_CFG_PAGESIZE_PS2048_64 (0x02 << SMC_CFG_PAGESIZE_SHIFT)
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#define SMC_CFG_PAGESIZE_PS4096_128 (0x03 << SMC_CFG_PAGESIZE_SHIFT)
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/* --- SMC NFC Control Register (SMC_CTRL) --------------------------------- */
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/* NAND Flash Controller Disable */
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#define SMC_CTRL_NFCDIS (1 << 1)
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/* NAND Flash Controller Enable */
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#define SMC_CTRL_NFCEN (1 << 0)
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/* --- SMC NFC Status Register (SMC_SR) ------------------------------------ */
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/* Ready/Busy Line 0 Edge Detected */
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#define SMC_SR_RB_EDGE0 (1 << 24)
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/* NFC Access Size Error */
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#define SMC_SR_NFCASE (1 << 23)
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/* Accessing While Busy */
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#define SMC_SR_AWB (1 << 22)
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/* Undefined Area Error */
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#define SMC_SR_UNDEF (1 << 21)
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/* Data Timeout Error */
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#define SMC_SR_DTOE (1 << 20)
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/* Command Done */
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#define SMC_SR_CMDDONE (1 << 17)
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/* NFC Data Transfer Terminated */
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#define SMC_SR_XFRDONE (1 << 16)
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/* NFC Chip Select ID */
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#define SMC_SR_NFCSID_SHIFT 12
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#define SMC_SR_NFCSID_MASK (0x07 << SMC_SR_NFCSID_SHIFT)
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/* NFC Write/Read Operation */
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#define SMC_SR_NFCWR (1 << 11)
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/* NFC Busy */
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#define SMC_SR_NFCBUSY (1 << 8)
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/* Selected Ready Busy Falling Edge Detected */
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#define SMC_SR_RB_FALL (1 << 5)
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/* Selected Ready Busy Rising Edge Detected */
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#define SMC_SR_RB_RISE (1 << 4)
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/* NAND Flash Controller status */
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#define SMC_SR_SMCSTS (1 << 0)
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/* --- SMC NFC Interrupt Enable Register (SMC_IER) ------------------------- */
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/* Ready/Busy Line 0 Interrupt Enable */
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#define SMC_IER_RB_EDGE0 (1 << 24)
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/* NFC Access Size Error Interrupt Enable */
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#define SMC_IER_NFCASE (1 << 23)
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/* Accessing While Busy Interrupt Enable */
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#define SMC_IER_AWB (1 << 22)
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/* Undefined Area Access Interrupt Enable */
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#define SMC_IER_UNDEF (1 << 21)
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/* Data Timeout Error Interrupt Enable */
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#define SMC_IER_DTOE (1 << 20)
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/* Command Done Interrupt Enable */
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#define SMC_IER_CMDDONE (1 << 17)
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/* Transfer Done Interrupt Enable */
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#define SMC_IER_XFRDONE (1 << 16)
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/* Ready Busy Falling Edge Detection Interrupt Enable */
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#define SMC_IER_RB_FALL (1 << 5)
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/* Ready Busy Rising Edge Detection Interrupt Enable */
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#define SMC_IER_RB_RISE (1 << 4)
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/* --- SMC NFC Interrupt Disable Register (SMC_IDR) ------------------------ */
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/* Ready/Busy Line 0 Interrupt Disable */
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#define SMC_IDR_RB_EDGE0 (1 << 24)
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/* NFC Access Size Error Interrupt Disable */
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#define SMC_IDR_NFCASE (1 << 23)
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/* Accessing While Busy Interrupt Disable */
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#define SMC_IDR_AWB (1 << 22)
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/* Undefined Area Access Interrupt Disable */
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#define SMC_IDR_UNDEF (1 << 21)
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/* Data Timeout Error Interrupt Disable */
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#define SMC_IDR_DTOE (1 << 20)
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/* Command Done Interrupt Disable */
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#define SMC_IDR_CMDDONE (1 << 17)
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/* Transfer Done Interrupt Disable */
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#define SMC_IDR_XFRDONE (1 << 16)
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/* Ready Busy Falling Edge Detection Interrupt Disable */
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#define SMC_IDR_RB_FALL (1 << 5)
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/* Ready Busy Rising Edge Detection Interrupt Disable */
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#define SMC_IDR_RB_RISE (1 << 4)
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/* --- SMC NFC Interrupt Mask Register (SMC_IMR) --------------------------- */
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/* Ready/Busy Line 0 Interrupt Mask */
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#define SMC_IMR_RB_EDGE0 (1 << 24)
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/* NFC Access Size Error Interrupt Mask */
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#define SMC_IMR_NFCASE (1 << 23)
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/* Accessing While Busy Interrupt Mask */
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#define SMC_IMR_AWB (1 << 22)
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/* Undefined Area Access Interrupt Mask */
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#define SMC_IMR_UNDEF (1 << 21)
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/* Data Timeout Error Interrupt Mask */
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#define SMC_IMR_DTOE (1 << 20)
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/* Command Done Interrupt Mask */
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#define SMC_IMR_CMDDONE (1 << 17)
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/* Transfer Done Interrupt Mask */
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#define SMC_IMR_XFRDONE (1 << 16)
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/* Ready Busy Falling Edge Detection Interrupt Mask */
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#define SMC_IMR_RB_FALL (1 << 5)
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/* Ready Busy Rising Edge Detection Interrupt Mask */
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#define SMC_IMR_RB_RISE (1 << 4)
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/* --- SMC NFC Address Cycle Zero Register (SMC_ADDR) ---------------------- */
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/* NAND Flash Array Address cycle 0 */
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#define SMC_ADDR_ADDR_CYCLE0_SHIFT 0
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#define SMC_ADDR_ADDR_CYCLE0_MASK (0xFF << SMC_ADDR_ADDR_CYCLE0_SHIFT)
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/* --- SMC NFC Bank Register (SMC_BANK) ------------------------------------ */
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/* Bank Identifier */
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#define SMC_BANK_BANK_SHIFT 0
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#define SMC_BANK_BANK_MASK (0x07 << SMC_BANK_BANK_SHIFT)
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/* --- SMC ECC Control Register (SMC_ECC_CTRL) ----------------------------- */
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/* Software Reset */
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#define SMC_ECC_CTRL_SWRST (1 << 1)
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/* Reset ECC */
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#define SMC_ECC_CTRL_RST (1 << 0)
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/* --- SMC ECC MODE Register (SMC_ECC_MD) ---------------------------------- */
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/* Type of Correction */
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#define SMC_ECC_MD_TYPCORREC_SHIFT 4
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#define SMC_ECC_MD_TYPCORREC_MASK (0x03 << SMC_ECC_MD_TYPCORREC_SHIFT)
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/* Type of Correction Values */
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#define SMC_ECC_MD_TYPCORREC_CPAGE (0x00 << SMC_ECC_MD_TYPCORREC_SHIFT)
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#define SMC_ECC_MD_TYPCORREC_C256B (0x01 << SMC_ECC_MD_TYPCORREC_SHIFT)
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#define SMC_ECC_MD_TYPCORREC_C512B (0x02 << SMC_ECC_MD_TYPCORREC_SHIFT)
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/* ECC Page Size */
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#define SMC_ECC_MD_ECC_PAGESIZE_SHIFT 0
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#define SMC_ECC_MD_ECC_PAGESIZE_MASK (0x03 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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/* ECC Page Size Values */
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#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x00 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x01 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x02 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x03 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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/* --- SMC ECC Status Register 1 (SMC_ECC_SR1) ----------------------------- */
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/* currently unimplemented */
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/* --- SMC ECC Status Register 2 (SMC_ECC_SR2) ----------------------------- */
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/* currently unimplemented */
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/* --- SMC ECC Parity Register 0 (SMC_ECC_PR0) ----------------------------- */
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/* currently unimplemented */
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/* --- SMC ECC Parity Register 1 (SMC_ECC_PR1) ----------------------------- */
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/* currently unimplemented */
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/* --- SMC ECC Parity Registers (SMC_ECC_PRx) ------------------------------ */
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/* currently unimplemented */
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/* --- SMC Setup Register (SMC_SETUPx) ------------------------------------- */
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/* NCS Setup length in Read access */
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#define SMC_SETUP_NCS_RD_SETUP_SHIFT 24
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#define SMC_SETUP_NCS_RD_SETUP_MASK (0x3F << SMC_SETUP_NCS_RD_SETUP_SHIFT)
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/* NRD Setup length */
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#define SMC_SETUP_NRD_SETUP_SHIFT 16
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#define SMC_SETUP_NRD_SETUP_MASK (0x3F << SMC_SETUP_NRD_SETUP_SHIFT)
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/* NCS Setup length in Write access */
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#define SMC_SETUP_NCS_WR_SETUP_SHIFT 8
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#define SMC_SETUP_NCS_WR_SETUP_MASK (0x3F << SMC_SETUP_NCS_WR_SETUP_SHIFT)
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/* NWE Setup Length */
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#define SMC_SETUP_NWE_SETUP_SHIFT 0
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#define SMC_SETUP_NWE_SETUP_MASK (0x3F << SMC_SETUP_NWE_SETUP_SHIFT)
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/* --- SMC Pulse Register (SMC_PULSEx) ------------------------------------- */
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/* NCS Pulse Length in READ Access */
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#define SMC_PULSE_NCS_RD_PULSE_SHIFT 24
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#define SMC_PULSE_NCS_RD_PULSE_MASK (0x3F << SMC_PULSE_NCS_RD_PULSE_SHIFT)
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/* NRD Pulse Length */
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#define SMC_PULSE_NRD_PULSE_SHIFT 16
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#define SMC_PULSE_NRD_PULSE_MASK (0x3F << SMC_PULSE_NRD_PULSE_SHIFT)
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/* NCS Pulse Length in WRITE Access */
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#define SMC_PULSE_NCS_WR_PULSE_SHIFT 8
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#define SMC_PULSE_NCS_WR_PULSE_MASK (0x3F << SMC_PULSE_NCS_WR_PULSE_SHIFT)
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/* NWE Pulse Length */
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#define SMC_PULSE_NWE_PULSE_SHIFT 0
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#define SMC_PULSE_NWE_PULSE_MASK (0x3F << SMC_PULSE_NWE_PULSE_SHIFT)
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/* --- SMC Cycle Register (SMC_CYCLEx) ------------------------------------- */
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/* Total Read Cycle Length */
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#define SMC_CYCLE_NRD_CYCLE_SHIFT 16
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#define SMC_CYCLE_NRD_CYCLE_MASK (0x1FF << SMC_CYCLE_NRD_CYCLE_SHIFT)
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/* Total Write Cycle Length */
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#define SMC_CYCLE_NWE_CYCLE_SHIFT 0
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#define SMC_CYCLE_NWE_CYCLE_MASK (0x1FF << SMC_CYCLE_NWE_CYCLE_SHIFT)
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/* --- SMC Timings Register (SMC_TIMINGSx) --------------------------------- */
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/* NAND Flash Selection */
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#define SMC_TIMINGS_NFSEL (1 << 31)
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/* Ready/Busy Line Selection */
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#define SMC_TIMINGS_RBNSEL_SHIFT 28
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#define SMC_TIMINGS_RBNSEL_MASK (0x07 << SMC_TIMINGS_RBNSEL_SHIFT)
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/* WEN High to REN to Busy */
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#define SMC_TIMINGS_TWB_SHIFT 24
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#define SMC_TIMINGS_TWB_MASK (0x0F << SMC_TIMINGS_TWB_SHIFT)
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/* Ready to REN Low Delay */
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#define SMC_TIMINGS_TRR_SHIFT 16
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#define SMC_TIMINGS_TRR_MASK (0x0F << SMC_TIMINGS_TRR_SHIFT)
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/* Off Chip Memory Scrambling Enable */
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#define SMC_TIMINGS_OCMS (1 << 12)
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/* ALE to REN Low Delay */
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#define SMC_TIMINGS_TAR_SHIFT 8
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#define SMC_TIMINGS_TAR_MASK (0x0F << SMC_TIMINGS_TAR_SHIFT)
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/* ALE to Data Start */
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#define SMC_TIMINGS_TADL_SHIFT 4
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#define SMC_TIMINGS_TADL_MASK (0x0F << SMC_TIMINGS_TADL_SHIFT)
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/* CLE to REN Low Delay */
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#define SMC_TIMINGS_TCLR_SHIFT 0
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#define SMC_TIMINGS_TCLR_MASK (0x0F << SMC_TIMINGS_TCLR_SHIFT)
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/* --- SMC Mode Register (SMC_MODEx) --------------------------------------- */
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/* TDF Optimization */
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#define SMC_MODE_TDF_MODE (1 << 20)
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/* Data Float Time */
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#define SMC_MODE_TDF_CYCLES_SHIFT 16
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#define SMC_MODE_TDF_CYCLES_MASK (0x0F << SMC_MODE_TDF_CYCLES_SHIFT)
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/* Data Bus Width */
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#define SMC_MODE_DBW (1 << 12)
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/* Data Bus Width Values */
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#define SMC_MODE_DBW_BIT_8 (0 << 12)
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#define SMC_MODE_DBW_BIT_16 (1 << 12)
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/* Byte Access Type */
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#define SMC_MODE_BAT (1 << 8)
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/* NWAIT Mode */
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#define SMC_MODE_EXNW_MODE_SHIFT 4
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#define SMC_MODE_EXNW_MODE_MASK (0x03 << SMC_MODE_EXNW_MODE_SHIFT)
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/* NWAIT Mode Values */
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#define SMC_MODE_EXNW_MODE_DISABLED (0x00 << SMC_MODE_EXNW_MODE_SHIFT)
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#define SMC_MODE_EXNW_MODE_FROZEN (0x02 << SMC_MODE_EXNW_MODE_SHIFT)
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#define SMC_MODE_EXNW_MODE_READY (0x03 << SMC_MODE_EXNW_MODE_SHIFT)
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/* Write Mode */
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#define SMC_MODE_WRITE_MODE (1 << 1)
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/* Read Mode */
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#define SMC_MODE_READ_MODE (1 << 0)
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/* --- SMC OCMS Register (SMC_OCMS) ---------------------------------------- */
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/* SRAM Scrambling Enable */
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#define SMC_OCMS_SRSE (1 << 1)
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/* Static Memory Controller Scrambling Enable */
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#define SMC_OCMS_SMSE (1 << 0)
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/* --- SMC Write Protection Control (SMC_WPCR) ----------------------------- */
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/* Write Protect Key */
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#define SMC_WPCR_WPKEY_SHIFT 8
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#define SMC_WPCR_WPKEY_KEY (0x534D43 << SMC_WPCR_WPKEY_SHIFT)
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/* Write Protect Enable */
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#define SMC_WPCR_WPEN (1 << 0)
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/* --- SMC Write Protection Status (SMC_WPSR) ------------------------------ */
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/* Write Protection Violation Source */
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#define SMC_WPSR_WP_VSRC_SHIFT 8
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#define SMC_WPSR_WP_VSRC_MASK (0xFFFF << SMC_WPSR_WP_VSRC_SHIFT)
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/* Write Protection Violation Status */
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#define SMC_WPSR_WP_VS_SHIFT 0
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#define SMC_WPSR_WP_VS_MASK (0x0F << SMC_WPSR_WP_VS_SHIFT)
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#endif
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