a444aa4476
Based on the f0 support, which has identical functionality, but with doxygen added. Bits renamed as they are only HSE prediv on some targets, and makes things more consistent with the f0. Fixes part of github issue #560
487 lines
9.9 KiB
C
487 lines
9.9 KiB
C
/** @defgroup rcc_file RCC
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*
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* @ingroup STM32F3xx
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*
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* @brief <b>libopencm3 STM32F3xx Reset and Clock Control</b>
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*
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* @version 1.0.0
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*
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* @date 11 July 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Modified by 2013 Fernando Cortes <fernando.corcam@gmail.com> (stm32f3)
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* Modified by 2013 Guillermo Rivera <memogrg@gmail.com> (stm32f3)
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/flash.h>
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#include <libopencm3/stm32/i2c.h>
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/* Set the default clock frequencies after reset. */
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uint32_t rcc_ahb_frequency = 8000000;
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uint32_t rcc_apb1_frequency = 8000000;
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uint32_t rcc_apb2_frequency = 8000000;
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const clock_scale_t hsi_8mhz[CLOCK_END] = {
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{ /* 44MHz */
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.pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X11,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
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.flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1WS,
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.apb1_frequency = 22000000,
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.apb2_frequency = 44000000,
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},
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{ /* 48MHz */
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.pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X12,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
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.flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1WS,
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.apb1_frequency = 24000000,
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.apb2_frequency = 48000000,
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},
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{ /* 64MHz */
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.pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X16,
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.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE1_DIV_2,
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.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
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.flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2WS,
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.apb1_frequency = 32000000,
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.apb2_frequency = 64000000,
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}
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};
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void rcc_osc_ready_int_clear(enum osc osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(enum osc osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(enum osc osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(enum osc osc)
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{
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switch (osc) {
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case PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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}
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cm3_assert_not_reached();
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}
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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void rcc_wait_for_osc_ready(enum osc osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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case HSI:
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while ((RCC_CR & RCC_CR_HSIRDY) == 0);
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break;
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case LSE:
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while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
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break;
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case LSI:
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
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break;
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}
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}
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void rcc_wait_for_osc_not_ready(enum osc osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) != 0);
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break;
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case HSE:
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while ((RCC_CR & RCC_CR_HSERDY) != 0);
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break;
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case HSI:
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while ((RCC_CR & RCC_CR_HSIRDY) != 0);
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break;
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case LSE:
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while ((RCC_BDCR & RCC_BDCR_LSERDY) != 0);
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break;
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case LSI:
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while ((RCC_CSR & RCC_CSR_LSIRDY) != 0);
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break;
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}
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}
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void rcc_wait_for_sysclk_status(enum osc osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
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break;
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case HSE:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
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break;
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case HSI:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
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break;
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default:
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/* Shouldn't be reached. */
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break;
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}
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}
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void rcc_osc_on(enum osc osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(enum osc osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
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case LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_osc_bypass_enable(enum osc osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR |= RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_BDCR |= RCC_BDCR_LSEBYP;
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break;
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case PLL:
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case HSI:
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case LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_osc_bypass_disable(enum osc osc)
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{
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switch (osc) {
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case HSE:
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RCC_CR &= ~RCC_CR_HSEBYP;
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break;
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case LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEBYP;
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break;
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case PLL:
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case HSI:
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case LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_set_sysclk_source(uint32_t clk)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | clk);
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}
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void rcc_set_pll_source(uint32_t pllsrc)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~RCC_CFGR_PLLSRC;
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RCC_CFGR = (reg32 | (pllsrc << 16));
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}
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void rcc_set_ppre2(uint32_t ppre2)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
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RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
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}
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void rcc_set_ppre1(uint32_t ppre1)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
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RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
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}
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void rcc_set_hpre(uint32_t hpre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
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RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
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}
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/**
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* Set PLL Source pre-divider **CAUTION**.
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* On some F3 devices, prediv only applies to HSE source. On others,
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* this is _after_ source selection. See also f0.
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* @param[in] prediv division by prediv+1 @ref rcc_cfgr2_prediv
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*/
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void rcc_set_prediv(uint32_t prediv)
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{
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RCC_CFGR2 = (RCC_CFGR2 & ~RCC_CFGR2_PREDIV) | prediv;
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}
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void rcc_set_pll_multiplier(uint32_t pll)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
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RCC_CFGR = (reg32 | (pll << RCC_CFGR_PLLMUL_SHIFT));
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}
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uint32_t rcc_get_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return (RCC_CFGR & 0x000c) >> 2;
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}
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void rcc_clock_setup_hsi(const clock_scale_t *clock)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* XXX: se cayo */
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rcc_wait_for_sysclk_status(HSI);
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rcc_osc_off(PLL);
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rcc_wait_for_osc_not_ready(PLL);
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rcc_set_pll_source(clock->pllsrc);
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rcc_set_pll_multiplier(clock->pll);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(clock->hpre);
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rcc_set_ppre2(clock->ppre2);
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rcc_set_ppre1(clock->ppre1);
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/* Configure flash settings. */
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flash_set_ws(clock->flash_config);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* XXX: se cayo */
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/* Wait for PLL clock to be selected. */
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rcc_wait_for_sysclk_status(PLL);
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/* Set the peripheral clock frequencies used. */
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rcc_apb1_frequency = clock->apb1_frequency;
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rcc_apb2_frequency = clock->apb2_frequency;
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}
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void rcc_backupdomain_reset(void)
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{
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/* Set the backup domain software reset. */
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RCC_BDCR |= RCC_BDCR_BDRST;
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/* Clear the backup domain software reset. */
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RCC_BDCR &= ~RCC_BDCR_BDRST;
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}
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void rcc_set_i2c_clock_hsi(uint32_t i2c)
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{
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if (i2c == I2C1) {
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RCC_CFGR3 &= ~RCC_CFGR3_I2C1SW;
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}
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if (i2c == I2C2) {
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RCC_CFGR3 &= ~RCC_CFGR3_I2C2SW;
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}
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}
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void rcc_set_i2c_clock_sysclk(uint32_t i2c)
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{
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if (i2c == I2C1) {
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RCC_CFGR3 |= RCC_CFGR3_I2C1SW;
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}
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if (i2c == I2C2) {
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RCC_CFGR3 |= RCC_CFGR3_I2C2SW;
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}
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}
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uint32_t rcc_get_i2c_clocks(void)
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{
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return RCC_CFGR3 & (RCC_CFGR3_I2C1SW | RCC_CFGR3_I2C2SW);
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}
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void rcc_usb_prescale_1_5(void)
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{
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RCC_CFGR &= ~RCC_CFGR_USBPRES;
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}
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void rcc_usb_prescale_1(void)
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{
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RCC_CFGR |= RCC_CFGR_USBPRES;
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}
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void rcc_adc_prescale(uint32_t prescale1, uint32_t prescale2)
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{
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uint32_t clear_mask = (RCC_CFGR2_ADCxPRES_MASK << RCC_CFGR2_ADC12PRES_SHIFT) |
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(RCC_CFGR2_ADCxPRES_MASK << RCC_CFGR2_ADC34PRES_SHIFT);
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uint32_t set = (prescale1 << RCC_CFGR2_ADC12PRES_SHIFT) |
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(prescale2 << RCC_CFGR2_ADC34PRES_SHIFT);
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RCC_CFGR2 &= ~(clear_mask);
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RCC_CFGR2 |= (set);
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}
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/**@}*/
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