1182 lines
42 KiB
C
1182 lines
42 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_USB_H
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#define LPC43XX_USB_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lpc43xx/memorymap.h>
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/* --- USB0 registers ------------------------------------------------------ */
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/* Device/host capability registers */
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/* Capability register length */
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#define USB0_CAPLENGTH MMIO32(USB0_BASE + 0x100)
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/* Host controller structural parameters */
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#define USB0_HCSPARAMS MMIO32(USB0_BASE + 0x104)
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/* Host controller capability parameters */
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#define USB0_HCCPARAMS MMIO32(USB0_BASE + 0x108)
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/* Device interface version number */
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#define USB0_DCIVERSION MMIO32(USB0_BASE + 0x120)
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/* Device controller capability parameters */
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#define USB0_DCCPARAMS MMIO32(USB0_BASE + 0x124)
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/* Device/host operational registers */
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/* USB command (device mode) */
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#define USB0_USBCMD_D MMIO32(USB0_BASE + 0x140)
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/* USB command (host mode) */
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#define USB0_USBCMD_H MMIO32(USB0_BASE + 0x140)
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/* USB status (device mode) */
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#define USB0_USBSTS_D MMIO32(USB0_BASE + 0x144)
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/* USB status (host mode) */
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#define USB0_USBSTS_H MMIO32(USB0_BASE + 0x144)
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/* USB interrupt enable (device mode) */
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#define USB0_USBINTR_D MMIO32(USB0_BASE + 0x148)
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/* USB interrupt enable (host mode) */
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#define USB0_USBINTR_H MMIO32(USB0_BASE + 0x148)
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/* USB frame index (device mode) */
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#define USB0_FRINDEX_D MMIO32(USB0_BASE + 0x14C)
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/* USB frame index (host mode) */
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#define USB0_FRINDEX_H MMIO32(USB0_BASE + 0x14C)
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/* USB device address (device mode) */
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#define USB0_DEVICEADDR MMIO32(USB0_BASE + 0x154)
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/* Frame list base address (host mode) */
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#define USB0_PERIODICLISTBASE MMIO32(USB0_BASE + 0x154)
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/* Address of endpoint list in memory */
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#define USB0_ENDPOINTLISTADDR MMIO32(USB0_BASE + 0x158)
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/* Asynchronous list address */
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#define USB0_ASYNCLISTADDR MMIO32(USB0_BASE + 0x158)
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/* Asynchronous buffer status for embedded TT (host mode) */
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#define USB0_TTCTRL MMIO32(USB0_BASE + 0x15C)
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/* Programmable burst size */
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#define USB0_BURSTSIZE MMIO32(USB0_BASE + 0x160)
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/* Host transmit pre-buffer packet tuning (host mode) */
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#define USB0_TXFILLTUNING MMIO32(USB0_BASE + 0x164)
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/* Length of virtual frame */
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#define USB0_BINTERVAL MMIO32(USB0_BASE + 0x174)
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/* Endpoint NAK (device mode) */
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#define USB0_ENDPTNAK MMIO32(USB0_BASE + 0x178)
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/* Endpoint NAK Enable (device mode) */
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#define USB0_ENDPTNAKEN MMIO32(USB0_BASE + 0x17C)
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/* Port 1 status/control (device mode) */
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#define USB0_PORTSC1_D MMIO32(USB0_BASE + 0x184)
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/* Port 1 status/control (host mode) */
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#define USB0_PORTSC1_H MMIO32(USB0_BASE + 0x184)
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/* OTG status and control */
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#define USB0_OTGSC MMIO32(USB0_BASE + 0x1A4)
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/* USB device mode (device mode) */
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#define USB0_USBMODE_D MMIO32(USB0_BASE + 0x1A8)
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/* USB device mode (host mode) */
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#define USB0_USBMODE_H MMIO32(USB0_BASE + 0x1A8)
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/* Device endpoint registers */
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/* Endpoint setup status */
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#define USB0_ENDPTSETUPSTAT MMIO32(USB0_BASE + 0x1AC)
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/* Endpoint initialization */
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#define USB0_ENDPTPRIME MMIO32(USB0_BASE + 0x1B0)
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/* Endpoint de-initialization */
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#define USB0_ENDPTFLUSH MMIO32(USB0_BASE + 0x1B4)
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/* Endpoint status */
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#define USB0_ENDPTSTAT MMIO32(USB0_BASE + 0x1B8)
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/* Endpoint complete */
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#define USB0_ENDPTCOMPLETE MMIO32(USB0_BASE + 0x1BC)
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/* Endpoint control */
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#define USB0_ENDPTCTRL(logical_ep) MMIO32(USB0_BASE + 0x1C0 + (logical_ep * 4))
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/* Endpoint control 0 */
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#define USB0_ENDPTCTRL0 USB0_ENDPTCTRL(0)
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/* Endpoint control 1 */
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#define USB0_ENDPTCTRL1 USB0_ENDPTCTRL(1)
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/* Endpoint control 2 */
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#define USB0_ENDPTCTRL2 USB0_ENDPTCTRL(2)
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/* Endpoint control 3 */
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#define USB0_ENDPTCTRL3 USB0_ENDPTCTRL(3)
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/* Endpoint control 4 */
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#define USB0_ENDPTCTRL4 USB0_ENDPTCTRL(4)
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/* Endpoint control 5 */
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#define USB0_ENDPTCTRL5 USB0_ENDPTCTRL(5)
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/* --- USB0_CAPLENGTH values ------------------------------------ */
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/* CAPLENGTH: Indicates offset to add to the register base address at the beginning of the Operational Register */
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#define USB0_CAPLENGTH_CAPLENGTH_SHIFT (0)
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#define USB0_CAPLENGTH_CAPLENGTH_MASK (0xff << USB0_CAPLENGTH_CAPLENGTH_SHIFT)
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#define USB0_CAPLENGTH_CAPLENGTH(x) ((x) << USB0_CAPLENGTH_CAPLENGTH_SHIFT)
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/* HCIVERSION: BCD encoding of the EHCI revision number supported by this host controller */
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#define USB0_CAPLENGTH_HCIVERSION_SHIFT (8)
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#define USB0_CAPLENGTH_HCIVERSION_MASK (0xffff << USB0_CAPLENGTH_HCIVERSION_SHIFT)
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#define USB0_CAPLENGTH_HCIVERSION(x) ((x) << USB0_CAPLENGTH_HCIVERSION_SHIFT)
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/* --- USB0_HCSPARAMS values ------------------------------------ */
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/* N_PORTS: Number of downstream ports */
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#define USB0_HCSPARAMS_N_PORTS_SHIFT (0)
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#define USB0_HCSPARAMS_N_PORTS_MASK (0xf << USB0_HCSPARAMS_N_PORTS_SHIFT)
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#define USB0_HCSPARAMS_N_PORTS(x) ((x) << USB0_HCSPARAMS_N_PORTS_SHIFT)
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/* PPC: Port Power Control */
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#define USB0_HCSPARAMS_PPC_SHIFT (4)
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#define USB0_HCSPARAMS_PPC (1 << USB0_HCSPARAMS_PPC_SHIFT)
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/* N_PCC: Number of Ports per Companion Controller */
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#define USB0_HCSPARAMS_N_PCC_SHIFT (8)
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#define USB0_HCSPARAMS_N_PCC_MASK (0xf << USB0_HCSPARAMS_N_PCC_SHIFT)
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#define USB0_HCSPARAMS_N_PCC(x) ((x) << USB0_HCSPARAMS_N_PCC_SHIFT)
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/* N_CC: Number of Companion Controller */
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#define USB0_HCSPARAMS_N_CC_SHIFT (12)
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#define USB0_HCSPARAMS_N_CC_MASK (0xf << USB0_HCSPARAMS_N_CC_SHIFT)
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#define USB0_HCSPARAMS_N_CC(x) ((x) << USB0_HCSPARAMS_N_CC_SHIFT)
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/* PI: Port indicators */
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#define USB0_HCSPARAMS_PI_SHIFT (16)
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#define USB0_HCSPARAMS_PI (1 << USB0_HCSPARAMS_PI_SHIFT)
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/* N_PTT: Number of Ports per Transaction Translator */
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#define USB0_HCSPARAMS_N_PTT_SHIFT (20)
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#define USB0_HCSPARAMS_N_PTT_MASK (0xf << USB0_HCSPARAMS_N_PTT_SHIFT)
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#define USB0_HCSPARAMS_N_PTT(x) ((x) << USB0_HCSPARAMS_N_PTT_SHIFT)
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/* N_TT: Number of Transaction Translators */
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#define USB0_HCSPARAMS_N_TT_SHIFT (24)
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#define USB0_HCSPARAMS_N_TT_MASK (0xf << USB0_HCSPARAMS_N_TT_SHIFT)
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#define USB0_HCSPARAMS_N_TT(x) ((x) << USB0_HCSPARAMS_N_TT_SHIFT)
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/* --- USB0_HCCPARAMS values ------------------------------------ */
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/* ADC: 64-bit Addressing Capability */
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#define USB0_HCCPARAMS_ADC_SHIFT (0)
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#define USB0_HCCPARAMS_ADC (1 << USB0_HCCPARAMS_ADC_SHIFT)
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/* PFL: Programmable Frame List Flag */
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#define USB0_HCCPARAMS_PFL_SHIFT (1)
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#define USB0_HCCPARAMS_PFL (1 << USB0_HCCPARAMS_PFL_SHIFT)
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/* ASP: Asynchronous Schedule Park Capability */
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#define USB0_HCCPARAMS_ASP_SHIFT (2)
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#define USB0_HCCPARAMS_ASP (1 << USB0_HCCPARAMS_ASP_SHIFT)
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/* IST: Isochronous Scheduling Threshold */
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#define USB0_HCCPARAMS_IST_SHIFT (4)
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#define USB0_HCCPARAMS_IST_MASK (0xf << USB0_HCCPARAMS_IST_SHIFT)
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#define USB0_HCCPARAMS_IST(x) ((x) << USB0_HCCPARAMS_IST_SHIFT)
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/* EECP: EHCI Extended Capabilities Pointer */
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#define USB0_HCCPARAMS_EECP_SHIFT (8)
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#define USB0_HCCPARAMS_EECP_MASK (0xf << USB0_HCCPARAMS_EECP_SHIFT)
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#define USB0_HCCPARAMS_EECP(x) ((x) << USB0_HCCPARAMS_EECP_SHIFT)
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/* --- USB0_DCCPARAMS values ------------------------------------ */
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/* DEN: Device Endpoint Number */
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#define USB0_DCCPARAMS_DEN_SHIFT (0)
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#define USB0_DCCPARAMS_DEN_MASK (0x1f << USB0_DCCPARAMS_DEN_SHIFT)
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#define USB0_DCCPARAMS_DEN(x) ((x) << USB0_DCCPARAMS_DEN_SHIFT)
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/* DC: Device Capable */
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#define USB0_DCCPARAMS_DC_SHIFT (7)
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#define USB0_DCCPARAMS_DC (1 << USB0_DCCPARAMS_DC_SHIFT)
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/* HC: Host Capable */
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#define USB0_DCCPARAMS_HC_SHIFT (8)
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#define USB0_DCCPARAMS_HC (1 << USB0_DCCPARAMS_HC_SHIFT)
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/* --- USB0_USBCMD_D values ------------------------------------- */
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/* RS: Run/Stop */
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#define USB0_USBCMD_D_RS_SHIFT (0)
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#define USB0_USBCMD_D_RS (1 << USB0_USBCMD_D_RS_SHIFT)
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/* RST: Controller reset */
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#define USB0_USBCMD_D_RST_SHIFT (1)
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#define USB0_USBCMD_D_RST (1 << USB0_USBCMD_D_RST_SHIFT)
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/* SUTW: Setup trip wire */
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#define USB0_USBCMD_D_SUTW_SHIFT (13)
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#define USB0_USBCMD_D_SUTW (1 << USB0_USBCMD_D_SUTW_SHIFT)
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/* ATDTW: Add dTD trip wire */
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#define USB0_USBCMD_D_ATDTW_SHIFT (14)
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#define USB0_USBCMD_D_ATDTW (1 << USB0_USBCMD_D_ATDTW_SHIFT)
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/* ITC: Interrupt threshold control */
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#define USB0_USBCMD_D_ITC_SHIFT (16)
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#define USB0_USBCMD_D_ITC_MASK (0xff << USB0_USBCMD_D_ITC_SHIFT)
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#define USB0_USBCMD_D_ITC(x) ((x) << USB0_USBCMD_D_ITC_SHIFT)
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/* --- USB0_USBCMD_H values ------------------------------------- */
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/* RS: Run/Stop */
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#define USB0_USBCMD_H_RS_SHIFT (0)
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#define USB0_USBCMD_H_RS (1 << USB0_USBCMD_H_RS_SHIFT)
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/* RST: Controller reset */
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#define USB0_USBCMD_H_RST_SHIFT (1)
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#define USB0_USBCMD_H_RST (1 << USB0_USBCMD_H_RST_SHIFT)
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/* FS0: Bit 0 of the Frame List Size bits */
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#define USB0_USBCMD_H_FS0_SHIFT (2)
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#define USB0_USBCMD_H_FS0 (1 << USB0_USBCMD_H_FS0_SHIFT)
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/* FS1: Bit 1 of the Frame List Size bits */
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#define USB0_USBCMD_H_FS1_SHIFT (3)
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#define USB0_USBCMD_H_FS1 (1 << USB0_USBCMD_H_FS1_SHIFT)
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/* PSE: This bit controls whether the host controller skips processing the periodic schedule */
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#define USB0_USBCMD_H_PSE_SHIFT (4)
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#define USB0_USBCMD_H_PSE (1 << USB0_USBCMD_H_PSE_SHIFT)
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/* ASE: This bit controls whether the host controller skips processing the asynchronous schedule */
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#define USB0_USBCMD_H_ASE_SHIFT (5)
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#define USB0_USBCMD_H_ASE (1 << USB0_USBCMD_H_ASE_SHIFT)
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/* IAA: This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule */
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#define USB0_USBCMD_H_IAA_SHIFT (6)
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#define USB0_USBCMD_H_IAA (1 << USB0_USBCMD_H_IAA_SHIFT)
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/* ASP1_0: Asynchronous schedule park mode */
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#define USB0_USBCMD_H_ASP1_0_SHIFT (8)
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#define USB0_USBCMD_H_ASP1_0_MASK (0x3 << USB0_USBCMD_H_ASP1_0_SHIFT)
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#define USB0_USBCMD_H_ASP1_0(x) ((x) << USB0_USBCMD_H_ASP1_0_SHIFT)
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/* ASPE: Asynchronous Schedule Park Mode Enable */
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#define USB0_USBCMD_H_ASPE_SHIFT (11)
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#define USB0_USBCMD_H_ASPE (1 << USB0_USBCMD_H_ASPE_SHIFT)
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/* FS2: Bit 2 of the Frame List Size bits */
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#define USB0_USBCMD_H_FS2_SHIFT (15)
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#define USB0_USBCMD_H_FS2 (1 << USB0_USBCMD_H_FS2_SHIFT)
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/* ITC: Interrupt threshold control */
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#define USB0_USBCMD_H_ITC_SHIFT (16)
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#define USB0_USBCMD_H_ITC_MASK (0xff << USB0_USBCMD_H_ITC_SHIFT)
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#define USB0_USBCMD_H_ITC(x) ((x) << USB0_USBCMD_H_ITC_SHIFT)
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/* --- USB0_USBSTS_D values ------------------------------------- */
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/* UI: USB interrupt */
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#define USB0_USBSTS_D_UI_SHIFT (0)
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#define USB0_USBSTS_D_UI (1 << USB0_USBSTS_D_UI_SHIFT)
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/* UEI: USB error interrupt */
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#define USB0_USBSTS_D_UEI_SHIFT (1)
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#define USB0_USBSTS_D_UEI (1 << USB0_USBSTS_D_UEI_SHIFT)
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/* PCI: Port change detect */
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#define USB0_USBSTS_D_PCI_SHIFT (2)
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#define USB0_USBSTS_D_PCI (1 << USB0_USBSTS_D_PCI_SHIFT)
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/* URI: USB reset received */
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#define USB0_USBSTS_D_URI_SHIFT (6)
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#define USB0_USBSTS_D_URI (1 << USB0_USBSTS_D_URI_SHIFT)
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/* SRI: SOF received */
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#define USB0_USBSTS_D_SRI_SHIFT (7)
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#define USB0_USBSTS_D_SRI (1 << USB0_USBSTS_D_SRI_SHIFT)
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/* SLI: DCSuspend */
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#define USB0_USBSTS_D_SLI_SHIFT (8)
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#define USB0_USBSTS_D_SLI (1 << USB0_USBSTS_D_SLI_SHIFT)
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/* NAKI: NAK interrupt bit */
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#define USB0_USBSTS_D_NAKI_SHIFT (16)
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#define USB0_USBSTS_D_NAKI (1 << USB0_USBSTS_D_NAKI_SHIFT)
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/* --- USB0_USBSTS_H values ------------------------------------- */
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/* UI: USB interrupt */
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#define USB0_USBSTS_H_UI_SHIFT (0)
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#define USB0_USBSTS_H_UI (1 << USB0_USBSTS_H_UI_SHIFT)
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/* UEI: USB error interrupt */
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#define USB0_USBSTS_H_UEI_SHIFT (1)
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#define USB0_USBSTS_H_UEI (1 << USB0_USBSTS_H_UEI_SHIFT)
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/* PCI: Port change detect */
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#define USB0_USBSTS_H_PCI_SHIFT (2)
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#define USB0_USBSTS_H_PCI (1 << USB0_USBSTS_H_PCI_SHIFT)
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/* FRI: Frame list roll-over */
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#define USB0_USBSTS_H_FRI_SHIFT (3)
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#define USB0_USBSTS_H_FRI (1 << USB0_USBSTS_H_FRI_SHIFT)
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/* AAI: Interrupt on async advance */
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#define USB0_USBSTS_H_AAI_SHIFT (5)
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#define USB0_USBSTS_H_AAI (1 << USB0_USBSTS_H_AAI_SHIFT)
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/* SRI: SOF received */
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#define USB0_USBSTS_H_SRI_SHIFT (7)
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#define USB0_USBSTS_H_SRI (1 << USB0_USBSTS_H_SRI_SHIFT)
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/* HCH: HCHalted */
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#define USB0_USBSTS_H_HCH_SHIFT (12)
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#define USB0_USBSTS_H_HCH (1 << USB0_USBSTS_H_HCH_SHIFT)
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/* RCL: Reclamation */
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#define USB0_USBSTS_H_RCL_SHIFT (13)
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#define USB0_USBSTS_H_RCL (1 << USB0_USBSTS_H_RCL_SHIFT)
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/* PS: Periodic schedule status */
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#define USB0_USBSTS_H_PS_SHIFT (14)
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#define USB0_USBSTS_H_PS (1 << USB0_USBSTS_H_PS_SHIFT)
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/* AS: Asynchronous schedule status */
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#define USB0_USBSTS_H_AS_SHIFT (15)
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#define USB0_USBSTS_H_AS (1 << USB0_USBSTS_H_AS_SHIFT)
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/* UAI: USB host asynchronous interrupt (USBHSTASYNCINT) */
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#define USB0_USBSTS_H_UAI_SHIFT (18)
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#define USB0_USBSTS_H_UAI (1 << USB0_USBSTS_H_UAI_SHIFT)
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/* UPI: USB host periodic interrupt (USBHSTPERINT) */
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#define USB0_USBSTS_H_UPI_SHIFT (19)
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#define USB0_USBSTS_H_UPI (1 << USB0_USBSTS_H_UPI_SHIFT)
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/* --- USB0_USBINTR_D values ------------------------------------ */
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/* UE: USB interrupt enable */
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#define USB0_USBINTR_D_UE_SHIFT (0)
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#define USB0_USBINTR_D_UE (1 << USB0_USBINTR_D_UE_SHIFT)
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/* UEE: USB error interrupt enable */
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#define USB0_USBINTR_D_UEE_SHIFT (1)
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#define USB0_USBINTR_D_UEE (1 << USB0_USBINTR_D_UEE_SHIFT)
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/* PCE: Port change detect enable */
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#define USB0_USBINTR_D_PCE_SHIFT (2)
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#define USB0_USBINTR_D_PCE (1 << USB0_USBINTR_D_PCE_SHIFT)
|
|
|
|
/* URE: USB reset enable */
|
|
#define USB0_USBINTR_D_URE_SHIFT (6)
|
|
#define USB0_USBINTR_D_URE (1 << USB0_USBINTR_D_URE_SHIFT)
|
|
|
|
/* SRE: SOF received enable */
|
|
#define USB0_USBINTR_D_SRE_SHIFT (7)
|
|
#define USB0_USBINTR_D_SRE (1 << USB0_USBINTR_D_SRE_SHIFT)
|
|
|
|
/* SLE: Sleep enable */
|
|
#define USB0_USBINTR_D_SLE_SHIFT (8)
|
|
#define USB0_USBINTR_D_SLE (1 << USB0_USBINTR_D_SLE_SHIFT)
|
|
|
|
/* NAKE: NAK interrupt enable */
|
|
#define USB0_USBINTR_D_NAKE_SHIFT (16)
|
|
#define USB0_USBINTR_D_NAKE (1 << USB0_USBINTR_D_NAKE_SHIFT)
|
|
|
|
/* --- USB0_USBINTR_H values ------------------------------------ */
|
|
|
|
/* UE: USB interrupt enable */
|
|
#define USB0_USBINTR_H_UE_SHIFT (0)
|
|
#define USB0_USBINTR_H_UE (1 << USB0_USBINTR_H_UE_SHIFT)
|
|
|
|
/* UEE: USB error interrupt enable */
|
|
#define USB0_USBINTR_H_UEE_SHIFT (1)
|
|
#define USB0_USBINTR_H_UEE (1 << USB0_USBINTR_H_UEE_SHIFT)
|
|
|
|
/* PCE: Port change detect enable */
|
|
#define USB0_USBINTR_H_PCE_SHIFT (2)
|
|
#define USB0_USBINTR_H_PCE (1 << USB0_USBINTR_H_PCE_SHIFT)
|
|
|
|
/* FRE: Frame list rollover enable */
|
|
#define USB0_USBINTR_H_FRE_SHIFT (3)
|
|
#define USB0_USBINTR_H_FRE (1 << USB0_USBINTR_H_FRE_SHIFT)
|
|
|
|
/* AAE: Interrupt on asynchronous advance enable */
|
|
#define USB0_USBINTR_H_AAE_SHIFT (5)
|
|
#define USB0_USBINTR_H_AAE (1 << USB0_USBINTR_H_AAE_SHIFT)
|
|
|
|
/* SRE: SOF received enable */
|
|
#define USB0_USBINTR_H_SRE_SHIFT (7)
|
|
#define USB0_USBINTR_H_SRE (1 << USB0_USBINTR_H_SRE_SHIFT)
|
|
|
|
/* UAIE: USB host asynchronous interrupt enable */
|
|
#define USB0_USBINTR_H_UAIE_SHIFT (18)
|
|
#define USB0_USBINTR_H_UAIE (1 << USB0_USBINTR_H_UAIE_SHIFT)
|
|
|
|
/* UPIA: USB host periodic interrupt enable */
|
|
#define USB0_USBINTR_H_UPIA_SHIFT (19)
|
|
#define USB0_USBINTR_H_UPIA (1 << USB0_USBINTR_H_UPIA_SHIFT)
|
|
|
|
/* --- USB0_FRINDEX_D values ------------------------------------ */
|
|
|
|
/* FRINDEX2_0: Current micro frame number */
|
|
#define USB0_FRINDEX_D_FRINDEX2_0_SHIFT (0)
|
|
#define USB0_FRINDEX_D_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_D_FRINDEX2_0_SHIFT)
|
|
#define USB0_FRINDEX_D_FRINDEX2_0(x) ((x) << USB0_FRINDEX_D_FRINDEX2_0_SHIFT)
|
|
|
|
/* FRINDEX13_3: Current frame number of the last frame transmitted */
|
|
#define USB0_FRINDEX_D_FRINDEX13_3_SHIFT (3)
|
|
#define USB0_FRINDEX_D_FRINDEX13_3_MASK (0x7ff << USB0_FRINDEX_D_FRINDEX13_3_SHIFT)
|
|
#define USB0_FRINDEX_D_FRINDEX13_3(x) ((x) << USB0_FRINDEX_D_FRINDEX13_3_SHIFT)
|
|
|
|
/* --- USB0_FRINDEX_H values ------------------------------------ */
|
|
|
|
/* FRINDEX2_0: Current micro frame number */
|
|
#define USB0_FRINDEX_H_FRINDEX2_0_SHIFT (0)
|
|
#define USB0_FRINDEX_H_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_H_FRINDEX2_0_SHIFT)
|
|
#define USB0_FRINDEX_H_FRINDEX2_0(x) ((x) << USB0_FRINDEX_H_FRINDEX2_0_SHIFT)
|
|
|
|
/* FRINDEX12_3: Frame list current index */
|
|
#define USB0_FRINDEX_H_FRINDEX12_3_SHIFT (3)
|
|
#define USB0_FRINDEX_H_FRINDEX12_3_MASK (0x3ff << USB0_FRINDEX_H_FRINDEX12_3_SHIFT)
|
|
#define USB0_FRINDEX_H_FRINDEX12_3(x) ((x) << USB0_FRINDEX_H_FRINDEX12_3_SHIFT)
|
|
|
|
/* --- USB0_DEVICEADDR values ----------------------------------- */
|
|
|
|
/* USBADRA: Device address advance */
|
|
#define USB0_DEVICEADDR_USBADRA_SHIFT (24)
|
|
#define USB0_DEVICEADDR_USBADRA (1 << USB0_DEVICEADDR_USBADRA_SHIFT)
|
|
|
|
/* USBADR: USB device address */
|
|
#define USB0_DEVICEADDR_USBADR_SHIFT (25)
|
|
#define USB0_DEVICEADDR_USBADR_MASK (0x7f << USB0_DEVICEADDR_USBADR_SHIFT)
|
|
#define USB0_DEVICEADDR_USBADR(x) ((x) << USB0_DEVICEADDR_USBADR_SHIFT)
|
|
|
|
/* --- USB0_PERIODICLISTBASE values ----------------------------- */
|
|
|
|
/* PERBASE31_12: Base Address (Low) */
|
|
#define USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT (12)
|
|
#define USB0_PERIODICLISTBASE_PERBASE31_12_MASK (0xfffff << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT)
|
|
#define USB0_PERIODICLISTBASE_PERBASE31_12(x) ((x) << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT)
|
|
|
|
/* --- USB0_ENDPOINTLISTADDR values ----------------------------- */
|
|
|
|
/* EPBASE31_11: Endpoint list pointer (low) */
|
|
#define USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT (11)
|
|
#define USB0_ENDPOINTLISTADDR_EPBASE31_11_MASK (0x1fffff << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT)
|
|
#define USB0_ENDPOINTLISTADDR_EPBASE31_11(x) ((x) << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT)
|
|
|
|
/* --- USB0_ASYNCLISTADDR values -------------------------------- */
|
|
|
|
/* ASYBASE31_5: Link pointer (Low) LPL */
|
|
#define USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT (5)
|
|
#define USB0_ASYNCLISTADDR_ASYBASE31_5_MASK (0x7ffffff << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT)
|
|
#define USB0_ASYNCLISTADDR_ASYBASE31_5(x) ((x) << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT)
|
|
|
|
/* --- USB0_TTCTRL values --------------------------------------- */
|
|
|
|
/* TTHA: Hub address when FS or LS device are connected directly */
|
|
#define USB0_TTCTRL_TTHA_SHIFT (24)
|
|
#define USB0_TTCTRL_TTHA_MASK (0x7f << USB0_TTCTRL_TTHA_SHIFT)
|
|
#define USB0_TTCTRL_TTHA(x) ((x) << USB0_TTCTRL_TTHA_SHIFT)
|
|
|
|
/* --- USB0_BURSTSIZE values ------------------------------------ */
|
|
|
|
/* RXPBURST: Programmable RX burst length */
|
|
#define USB0_BURSTSIZE_RXPBURST_SHIFT (0)
|
|
#define USB0_BURSTSIZE_RXPBURST_MASK (0xff << USB0_BURSTSIZE_RXPBURST_SHIFT)
|
|
#define USB0_BURSTSIZE_RXPBURST(x) ((x) << USB0_BURSTSIZE_RXPBURST_SHIFT)
|
|
|
|
/* TXPBURST: Programmable TX burst length */
|
|
#define USB0_BURSTSIZE_TXPBURST_SHIFT (8)
|
|
#define USB0_BURSTSIZE_TXPBURST_MASK (0xff << USB0_BURSTSIZE_TXPBURST_SHIFT)
|
|
#define USB0_BURSTSIZE_TXPBURST(x) ((x) << USB0_BURSTSIZE_TXPBURST_SHIFT)
|
|
|
|
/* --- USB0_TXFILLTUNING values --------------------------------- */
|
|
|
|
/* TXSCHOH: FIFO burst threshold */
|
|
#define USB0_TXFILLTUNING_TXSCHOH_SHIFT (0)
|
|
#define USB0_TXFILLTUNING_TXSCHOH_MASK (0xff << USB0_TXFILLTUNING_TXSCHOH_SHIFT)
|
|
#define USB0_TXFILLTUNING_TXSCHOH(x) ((x) << USB0_TXFILLTUNING_TXSCHOH_SHIFT)
|
|
|
|
/* TXSCHEATLTH: Scheduler health counter */
|
|
#define USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT (8)
|
|
#define USB0_TXFILLTUNING_TXSCHEATLTH_MASK (0x1f << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT)
|
|
#define USB0_TXFILLTUNING_TXSCHEATLTH(x) ((x) << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT)
|
|
|
|
/* TXFIFOTHRES: Scheduler overhead */
|
|
#define USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT (16)
|
|
#define USB0_TXFILLTUNING_TXFIFOTHRES_MASK (0x3f << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT)
|
|
#define USB0_TXFILLTUNING_TXFIFOTHRES(x) ((x) << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT)
|
|
|
|
/* --- USB0_BINTERVAL values ------------------------------------ */
|
|
|
|
/* BINT: bInterval value */
|
|
#define USB0_BINTERVAL_BINT_SHIFT (0)
|
|
#define USB0_BINTERVAL_BINT_MASK (0xf << USB0_BINTERVAL_BINT_SHIFT)
|
|
#define USB0_BINTERVAL_BINT(x) ((x) << USB0_BINTERVAL_BINT_SHIFT)
|
|
|
|
/* --- USB0_ENDPTNAK values ------------------------------------- */
|
|
|
|
/* EPRN: Rx endpoint NAK */
|
|
#define USB0_ENDPTNAK_EPRN_SHIFT (0)
|
|
#define USB0_ENDPTNAK_EPRN_MASK (0x3f << USB0_ENDPTNAK_EPRN_SHIFT)
|
|
#define USB0_ENDPTNAK_EPRN(x) ((x) << USB0_ENDPTNAK_EPRN_SHIFT)
|
|
|
|
/* EPTN: Tx endpoint NAK */
|
|
#define USB0_ENDPTNAK_EPTN_SHIFT (16)
|
|
#define USB0_ENDPTNAK_EPTN_MASK (0x3f << USB0_ENDPTNAK_EPTN_SHIFT)
|
|
#define USB0_ENDPTNAK_EPTN(x) ((x) << USB0_ENDPTNAK_EPTN_SHIFT)
|
|
|
|
/* --- USB0_ENDPTNAKEN values ----------------------------------- */
|
|
|
|
/* EPRNE: Rx endpoint NAK enable */
|
|
#define USB0_ENDPTNAKEN_EPRNE_SHIFT (0)
|
|
#define USB0_ENDPTNAKEN_EPRNE_MASK (0x3f << USB0_ENDPTNAKEN_EPRNE_SHIFT)
|
|
#define USB0_ENDPTNAKEN_EPRNE(x) ((x) << USB0_ENDPTNAKEN_EPRNE_SHIFT)
|
|
|
|
/* EPTNE: Tx endpoint NAK */
|
|
#define USB0_ENDPTNAKEN_EPTNE_SHIFT (16)
|
|
#define USB0_ENDPTNAKEN_EPTNE_MASK (0x3f << USB0_ENDPTNAKEN_EPTNE_SHIFT)
|
|
#define USB0_ENDPTNAKEN_EPTNE(x) ((x) << USB0_ENDPTNAKEN_EPTNE_SHIFT)
|
|
|
|
/* --- USB0_PORTSC1_D values ------------------------------------ */
|
|
|
|
/* CCS: Current connect status */
|
|
#define USB0_PORTSC1_D_CCS_SHIFT (0)
|
|
#define USB0_PORTSC1_D_CCS (1 << USB0_PORTSC1_D_CCS_SHIFT)
|
|
|
|
/* PE: Port enable */
|
|
#define USB0_PORTSC1_D_PE_SHIFT (2)
|
|
#define USB0_PORTSC1_D_PE (1 << USB0_PORTSC1_D_PE_SHIFT)
|
|
|
|
/* PEC: Port enable/disable change */
|
|
#define USB0_PORTSC1_D_PEC_SHIFT (3)
|
|
#define USB0_PORTSC1_D_PEC (1 << USB0_PORTSC1_D_PEC_SHIFT)
|
|
|
|
/* FPR: Force port resume */
|
|
#define USB0_PORTSC1_D_FPR_SHIFT (6)
|
|
#define USB0_PORTSC1_D_FPR (1 << USB0_PORTSC1_D_FPR_SHIFT)
|
|
|
|
/* SUSP: Suspend */
|
|
#define USB0_PORTSC1_D_SUSP_SHIFT (7)
|
|
#define USB0_PORTSC1_D_SUSP (1 << USB0_PORTSC1_D_SUSP_SHIFT)
|
|
|
|
/* PR: Port reset */
|
|
#define USB0_PORTSC1_D_PR_SHIFT (8)
|
|
#define USB0_PORTSC1_D_PR (1 << USB0_PORTSC1_D_PR_SHIFT)
|
|
|
|
/* HSP: High-speed status */
|
|
#define USB0_PORTSC1_D_HSP_SHIFT (9)
|
|
#define USB0_PORTSC1_D_HSP (1 << USB0_PORTSC1_D_HSP_SHIFT)
|
|
|
|
/* PIC1_0: Port indicator control */
|
|
#define USB0_PORTSC1_D_PIC1_0_SHIFT (14)
|
|
#define USB0_PORTSC1_D_PIC1_0_MASK (0x3 << USB0_PORTSC1_D_PIC1_0_SHIFT)
|
|
#define USB0_PORTSC1_D_PIC1_0(x) ((x) << USB0_PORTSC1_D_PIC1_0_SHIFT)
|
|
|
|
/* PTC3_0: Port test control */
|
|
#define USB0_PORTSC1_D_PTC3_0_SHIFT (16)
|
|
#define USB0_PORTSC1_D_PTC3_0_MASK (0xf << USB0_PORTSC1_D_PTC3_0_SHIFT)
|
|
#define USB0_PORTSC1_D_PTC3_0(x) ((x) << USB0_PORTSC1_D_PTC3_0_SHIFT)
|
|
|
|
/* PHCD: PHY low power suspend - clock disable (PLPSCD) */
|
|
#define USB0_PORTSC1_D_PHCD_SHIFT (23)
|
|
#define USB0_PORTSC1_D_PHCD (1 << USB0_PORTSC1_D_PHCD_SHIFT)
|
|
|
|
/* PFSC: Port force full speed connect */
|
|
#define USB0_PORTSC1_D_PFSC_SHIFT (24)
|
|
#define USB0_PORTSC1_D_PFSC (1 << USB0_PORTSC1_D_PFSC_SHIFT)
|
|
|
|
/* PSPD: Port speed */
|
|
#define USB0_PORTSC1_D_PSPD_SHIFT (26)
|
|
#define USB0_PORTSC1_D_PSPD_MASK (0x3 << USB0_PORTSC1_D_PSPD_SHIFT)
|
|
#define USB0_PORTSC1_D_PSPD(x) ((x) << USB0_PORTSC1_D_PSPD_SHIFT)
|
|
|
|
/* --- USB0_PORTSC1_H values ------------------------------------ */
|
|
|
|
/* CCS: Current connect status */
|
|
#define USB0_PORTSC1_H_CCS_SHIFT (0)
|
|
#define USB0_PORTSC1_H_CCS (1 << USB0_PORTSC1_H_CCS_SHIFT)
|
|
|
|
/* CSC: Connect status change */
|
|
#define USB0_PORTSC1_H_CSC_SHIFT (1)
|
|
#define USB0_PORTSC1_H_CSC (1 << USB0_PORTSC1_H_CSC_SHIFT)
|
|
|
|
/* PE: Port enable */
|
|
#define USB0_PORTSC1_H_PE_SHIFT (2)
|
|
#define USB0_PORTSC1_H_PE (1 << USB0_PORTSC1_H_PE_SHIFT)
|
|
|
|
/* PEC: Port disable/enable change */
|
|
#define USB0_PORTSC1_H_PEC_SHIFT (3)
|
|
#define USB0_PORTSC1_H_PEC (1 << USB0_PORTSC1_H_PEC_SHIFT)
|
|
|
|
/* OCA: Over-current active */
|
|
#define USB0_PORTSC1_H_OCA_SHIFT (4)
|
|
#define USB0_PORTSC1_H_OCA (1 << USB0_PORTSC1_H_OCA_SHIFT)
|
|
|
|
/* OCC: Over-current change */
|
|
#define USB0_PORTSC1_H_OCC_SHIFT (5)
|
|
#define USB0_PORTSC1_H_OCC (1 << USB0_PORTSC1_H_OCC_SHIFT)
|
|
|
|
/* FPR: Force port resume */
|
|
#define USB0_PORTSC1_H_FPR_SHIFT (6)
|
|
#define USB0_PORTSC1_H_FPR (1 << USB0_PORTSC1_H_FPR_SHIFT)
|
|
|
|
/* SUSP: Suspend */
|
|
#define USB0_PORTSC1_H_SUSP_SHIFT (7)
|
|
#define USB0_PORTSC1_H_SUSP (1 << USB0_PORTSC1_H_SUSP_SHIFT)
|
|
|
|
/* PR: Port reset */
|
|
#define USB0_PORTSC1_H_PR_SHIFT (8)
|
|
#define USB0_PORTSC1_H_PR (1 << USB0_PORTSC1_H_PR_SHIFT)
|
|
|
|
/* HSP: High-speed status */
|
|
#define USB0_PORTSC1_H_HSP_SHIFT (9)
|
|
#define USB0_PORTSC1_H_HSP (1 << USB0_PORTSC1_H_HSP_SHIFT)
|
|
|
|
/* LS: Line status */
|
|
#define USB0_PORTSC1_H_LS_SHIFT (10)
|
|
#define USB0_PORTSC1_H_LS_MASK (0x3 << USB0_PORTSC1_H_LS_SHIFT)
|
|
#define USB0_PORTSC1_H_LS(x) ((x) << USB0_PORTSC1_H_LS_SHIFT)
|
|
|
|
/* PP: Port power control */
|
|
#define USB0_PORTSC1_H_PP_SHIFT (12)
|
|
#define USB0_PORTSC1_H_PP (1 << USB0_PORTSC1_H_PP_SHIFT)
|
|
|
|
/* PIC1_0: Port indicator control */
|
|
#define USB0_PORTSC1_H_PIC1_0_SHIFT (14)
|
|
#define USB0_PORTSC1_H_PIC1_0_MASK (0x3 << USB0_PORTSC1_H_PIC1_0_SHIFT)
|
|
#define USB0_PORTSC1_H_PIC1_0(x) ((x) << USB0_PORTSC1_H_PIC1_0_SHIFT)
|
|
|
|
/* PTC3_0: Port test control */
|
|
#define USB0_PORTSC1_H_PTC3_0_SHIFT (16)
|
|
#define USB0_PORTSC1_H_PTC3_0_MASK (0xf << USB0_PORTSC1_H_PTC3_0_SHIFT)
|
|
#define USB0_PORTSC1_H_PTC3_0(x) ((x) << USB0_PORTSC1_H_PTC3_0_SHIFT)
|
|
|
|
/* WKCN: Wake on connect enable (WKCNNT_E) */
|
|
#define USB0_PORTSC1_H_WKCN_SHIFT (20)
|
|
#define USB0_PORTSC1_H_WKCN (1 << USB0_PORTSC1_H_WKCN_SHIFT)
|
|
|
|
/* WKDC: Wake on disconnect enable (WKDSCNNT_E) */
|
|
#define USB0_PORTSC1_H_WKDC_SHIFT (21)
|
|
#define USB0_PORTSC1_H_WKDC (1 << USB0_PORTSC1_H_WKDC_SHIFT)
|
|
|
|
/* WKOC: Wake on over-current enable (WKOC_E) */
|
|
#define USB0_PORTSC1_H_WKOC_SHIFT (22)
|
|
#define USB0_PORTSC1_H_WKOC (1 << USB0_PORTSC1_H_WKOC_SHIFT)
|
|
|
|
/* PHCD: PHY low power suspend - clock disable (PLPSCD) */
|
|
#define USB0_PORTSC1_H_PHCD_SHIFT (23)
|
|
#define USB0_PORTSC1_H_PHCD (1 << USB0_PORTSC1_H_PHCD_SHIFT)
|
|
|
|
/* PFSC: Port force full speed connect */
|
|
#define USB0_PORTSC1_H_PFSC_SHIFT (24)
|
|
#define USB0_PORTSC1_H_PFSC (1 << USB0_PORTSC1_H_PFSC_SHIFT)
|
|
|
|
/* PSPD: Port speed */
|
|
#define USB0_PORTSC1_H_PSPD_SHIFT (26)
|
|
#define USB0_PORTSC1_H_PSPD_MASK (0x3 << USB0_PORTSC1_H_PSPD_SHIFT)
|
|
#define USB0_PORTSC1_H_PSPD(x) ((x) << USB0_PORTSC1_H_PSPD_SHIFT)
|
|
|
|
/* --- USB0_OTGSC values ---------------------------------------- */
|
|
|
|
/* VD: VBUS_Discharge */
|
|
#define USB0_OTGSC_VD_SHIFT (0)
|
|
#define USB0_OTGSC_VD (1 << USB0_OTGSC_VD_SHIFT)
|
|
|
|
/* VC: VBUS_Charge */
|
|
#define USB0_OTGSC_VC_SHIFT (1)
|
|
#define USB0_OTGSC_VC (1 << USB0_OTGSC_VC_SHIFT)
|
|
|
|
/* HAAR: Hardware assist auto_reset */
|
|
#define USB0_OTGSC_HAAR_SHIFT (2)
|
|
#define USB0_OTGSC_HAAR (1 << USB0_OTGSC_HAAR_SHIFT)
|
|
|
|
/* OT: OTG termination */
|
|
#define USB0_OTGSC_OT_SHIFT (3)
|
|
#define USB0_OTGSC_OT (1 << USB0_OTGSC_OT_SHIFT)
|
|
|
|
/* DP: Data pulsing */
|
|
#define USB0_OTGSC_DP_SHIFT (4)
|
|
#define USB0_OTGSC_DP (1 << USB0_OTGSC_DP_SHIFT)
|
|
|
|
/* IDPU: ID pull-up */
|
|
#define USB0_OTGSC_IDPU_SHIFT (5)
|
|
#define USB0_OTGSC_IDPU (1 << USB0_OTGSC_IDPU_SHIFT)
|
|
|
|
/* HADP: Hardware assist data pulse */
|
|
#define USB0_OTGSC_HADP_SHIFT (6)
|
|
#define USB0_OTGSC_HADP (1 << USB0_OTGSC_HADP_SHIFT)
|
|
|
|
/* HABA: Hardware assist B-disconnect to A-connect */
|
|
#define USB0_OTGSC_HABA_SHIFT (7)
|
|
#define USB0_OTGSC_HABA (1 << USB0_OTGSC_HABA_SHIFT)
|
|
|
|
/* ID: USB ID */
|
|
#define USB0_OTGSC_ID_SHIFT (8)
|
|
#define USB0_OTGSC_ID (1 << USB0_OTGSC_ID_SHIFT)
|
|
|
|
/* AVV: A-VBUS valid */
|
|
#define USB0_OTGSC_AVV_SHIFT (9)
|
|
#define USB0_OTGSC_AVV (1 << USB0_OTGSC_AVV_SHIFT)
|
|
|
|
/* ASV: A-session valid */
|
|
#define USB0_OTGSC_ASV_SHIFT (10)
|
|
#define USB0_OTGSC_ASV (1 << USB0_OTGSC_ASV_SHIFT)
|
|
|
|
/* BSV: B-session valid */
|
|
#define USB0_OTGSC_BSV_SHIFT (11)
|
|
#define USB0_OTGSC_BSV (1 << USB0_OTGSC_BSV_SHIFT)
|
|
|
|
/* BSE: B-session end */
|
|
#define USB0_OTGSC_BSE_SHIFT (12)
|
|
#define USB0_OTGSC_BSE (1 << USB0_OTGSC_BSE_SHIFT)
|
|
|
|
/* MS1T: 1 millisecond timer toggle */
|
|
#define USB0_OTGSC_MS1T_SHIFT (13)
|
|
#define USB0_OTGSC_MS1T (1 << USB0_OTGSC_MS1T_SHIFT)
|
|
|
|
/* DPS: Data bus pulsing status */
|
|
#define USB0_OTGSC_DPS_SHIFT (14)
|
|
#define USB0_OTGSC_DPS (1 << USB0_OTGSC_DPS_SHIFT)
|
|
|
|
/* IDIS: USB ID interrupt status */
|
|
#define USB0_OTGSC_IDIS_SHIFT (16)
|
|
#define USB0_OTGSC_IDIS (1 << USB0_OTGSC_IDIS_SHIFT)
|
|
|
|
/* AVVIS: A-VBUS valid interrupt status */
|
|
#define USB0_OTGSC_AVVIS_SHIFT (17)
|
|
#define USB0_OTGSC_AVVIS (1 << USB0_OTGSC_AVVIS_SHIFT)
|
|
|
|
/* ASVIS: A-Session valid interrupt status */
|
|
#define USB0_OTGSC_ASVIS_SHIFT (18)
|
|
#define USB0_OTGSC_ASVIS (1 << USB0_OTGSC_ASVIS_SHIFT)
|
|
|
|
/* BSVIS: B-Session valid interrupt status */
|
|
#define USB0_OTGSC_BSVIS_SHIFT (19)
|
|
#define USB0_OTGSC_BSVIS (1 << USB0_OTGSC_BSVIS_SHIFT)
|
|
|
|
/* BSEIS: B-Session end interrupt status */
|
|
#define USB0_OTGSC_BSEIS_SHIFT (20)
|
|
#define USB0_OTGSC_BSEIS (1 << USB0_OTGSC_BSEIS_SHIFT)
|
|
|
|
/* MS1S: 1 millisecond timer interrupt status */
|
|
#define USB0_OTGSC_MS1S_SHIFT (21)
|
|
#define USB0_OTGSC_MS1S (1 << USB0_OTGSC_MS1S_SHIFT)
|
|
|
|
/* DPIS: Data pulse interrupt status */
|
|
#define USB0_OTGSC_DPIS_SHIFT (22)
|
|
#define USB0_OTGSC_DPIS (1 << USB0_OTGSC_DPIS_SHIFT)
|
|
|
|
/* IDIE: USB ID interrupt enable */
|
|
#define USB0_OTGSC_IDIE_SHIFT (24)
|
|
#define USB0_OTGSC_IDIE (1 << USB0_OTGSC_IDIE_SHIFT)
|
|
|
|
/* AVVIE: A-VBUS valid interrupt enable */
|
|
#define USB0_OTGSC_AVVIE_SHIFT (25)
|
|
#define USB0_OTGSC_AVVIE (1 << USB0_OTGSC_AVVIE_SHIFT)
|
|
|
|
/* ASVIE: A-session valid interrupt enable */
|
|
#define USB0_OTGSC_ASVIE_SHIFT (26)
|
|
#define USB0_OTGSC_ASVIE (1 << USB0_OTGSC_ASVIE_SHIFT)
|
|
|
|
/* BSVIE: B-session valid interrupt enable */
|
|
#define USB0_OTGSC_BSVIE_SHIFT (27)
|
|
#define USB0_OTGSC_BSVIE (1 << USB0_OTGSC_BSVIE_SHIFT)
|
|
|
|
/* BSEIE: B-session end interrupt enable */
|
|
#define USB0_OTGSC_BSEIE_SHIFT (28)
|
|
#define USB0_OTGSC_BSEIE (1 << USB0_OTGSC_BSEIE_SHIFT)
|
|
|
|
/* MS1E: 1 millisecond timer interrupt enable */
|
|
#define USB0_OTGSC_MS1E_SHIFT (29)
|
|
#define USB0_OTGSC_MS1E (1 << USB0_OTGSC_MS1E_SHIFT)
|
|
|
|
/* DPIE: Data pulse interrupt enable */
|
|
#define USB0_OTGSC_DPIE_SHIFT (30)
|
|
#define USB0_OTGSC_DPIE (1 << USB0_OTGSC_DPIE_SHIFT)
|
|
|
|
/* --- USB0_USBMODE_D values ------------------------------------ */
|
|
|
|
/* CM1_0: Controller mode */
|
|
#define USB0_USBMODE_D_CM1_0_SHIFT (0)
|
|
#define USB0_USBMODE_D_CM1_0_MASK (0x3 << USB0_USBMODE_D_CM1_0_SHIFT)
|
|
#define USB0_USBMODE_D_CM1_0(x) ((x) << USB0_USBMODE_D_CM1_0_SHIFT)
|
|
|
|
/* ES: Endian select */
|
|
#define USB0_USBMODE_D_ES_SHIFT (2)
|
|
#define USB0_USBMODE_D_ES (1 << USB0_USBMODE_D_ES_SHIFT)
|
|
|
|
/* SLOM: Setup Lockout mode */
|
|
#define USB0_USBMODE_D_SLOM_SHIFT (3)
|
|
#define USB0_USBMODE_D_SLOM (1 << USB0_USBMODE_D_SLOM_SHIFT)
|
|
|
|
/* SDIS: Setup Lockout mode */
|
|
#define USB0_USBMODE_D_SDIS_SHIFT (4)
|
|
#define USB0_USBMODE_D_SDIS (1 << USB0_USBMODE_D_SDIS_SHIFT)
|
|
|
|
/* --- USB0_USBMODE_H values ------------------------------------ */
|
|
|
|
/* CM: Controller mode */
|
|
#define USB0_USBMODE_H_CM_SHIFT (0)
|
|
#define USB0_USBMODE_H_CM_MASK (0x3 << USB0_USBMODE_H_CM_SHIFT)
|
|
#define USB0_USBMODE_H_CM(x) ((x) << USB0_USBMODE_H_CM_SHIFT)
|
|
|
|
/* ES: Endian select */
|
|
#define USB0_USBMODE_H_ES_SHIFT (2)
|
|
#define USB0_USBMODE_H_ES (1 << USB0_USBMODE_H_ES_SHIFT)
|
|
|
|
/* SDIS: Stream disable mode */
|
|
#define USB0_USBMODE_H_SDIS_SHIFT (4)
|
|
#define USB0_USBMODE_H_SDIS (1 << USB0_USBMODE_H_SDIS_SHIFT)
|
|
|
|
/* VBPS: VBUS power select */
|
|
#define USB0_USBMODE_H_VBPS_SHIFT (5)
|
|
#define USB0_USBMODE_H_VBPS (1 << USB0_USBMODE_H_VBPS_SHIFT)
|
|
|
|
/* --- USB0_ENDPTSETUPSTAT values ------------------------------- */
|
|
|
|
/* ENDPSETUPSTAT: Setup endpoint status for logical endpoints 0 to 5 */
|
|
#define USB0_ENDPTSETUPSTAT_ENDPSETUPSTAT_SHIFT (0)
|
|
#define USB0_ENDPTSETUPSTAT_ENDPSETUPSTAT_MASK (0x3f << USB0_ENDPTSETUPSTAT_ENDPSETUPSTAT_SHIFT)
|
|
#define USB0_ENDPTSETUPSTAT_ENDPSETUPSTAT(x) ((x) << USB0_ENDPTSETUPSTAT_ENDPSETUPSTAT_SHIFT)
|
|
|
|
/* --- USB0_ENDPTPRIME values ----------------------------------- */
|
|
|
|
/* PERB: Prime endpoint receive buffer for physical OUT endpoints 5 to 0 */
|
|
#define USB0_ENDPTPRIME_PERB_SHIFT (0)
|
|
#define USB0_ENDPTPRIME_PERB_MASK (0x3f << USB0_ENDPTPRIME_PERB_SHIFT)
|
|
#define USB0_ENDPTPRIME_PERB(x) ((x) << USB0_ENDPTPRIME_PERB_SHIFT)
|
|
|
|
/* PETB: Prime endpoint transmit buffer for physical IN endpoints 5 to 0 */
|
|
#define USB0_ENDPTPRIME_PETB_SHIFT (16)
|
|
#define USB0_ENDPTPRIME_PETB_MASK (0x3f << USB0_ENDPTPRIME_PETB_SHIFT)
|
|
#define USB0_ENDPTPRIME_PETB(x) ((x) << USB0_ENDPTPRIME_PETB_SHIFT)
|
|
|
|
/* --- USB0_ENDPTFLUSH values ----------------------------------- */
|
|
|
|
/* FERB: Flush endpoint receive buffer for physical OUT endpoints 5 to 0 */
|
|
#define USB0_ENDPTFLUSH_FERB_SHIFT (0)
|
|
#define USB0_ENDPTFLUSH_FERB_MASK (0x3f << USB0_ENDPTFLUSH_FERB_SHIFT)
|
|
#define USB0_ENDPTFLUSH_FERB(x) ((x) << USB0_ENDPTFLUSH_FERB_SHIFT)
|
|
|
|
/* FETB: Flush endpoint transmit buffer for physical IN endpoints 5 to 0 */
|
|
#define USB0_ENDPTFLUSH_FETB_SHIFT (16)
|
|
#define USB0_ENDPTFLUSH_FETB_MASK (0x3f << USB0_ENDPTFLUSH_FETB_SHIFT)
|
|
#define USB0_ENDPTFLUSH_FETB(x) ((x) << USB0_ENDPTFLUSH_FETB_SHIFT)
|
|
|
|
/* --- USB0_ENDPTSTAT values ------------------------------------ */
|
|
|
|
/* ERBR: Endpoint receive buffer ready for physical OUT endpoints 5 to 0 */
|
|
#define USB0_ENDPTSTAT_ERBR_SHIFT (0)
|
|
#define USB0_ENDPTSTAT_ERBR_MASK (0x3f << USB0_ENDPTSTAT_ERBR_SHIFT)
|
|
#define USB0_ENDPTSTAT_ERBR(x) ((x) << USB0_ENDPTSTAT_ERBR_SHIFT)
|
|
|
|
/* ETBR: Endpoint transmit buffer ready for physical IN endpoints 3 to 0 */
|
|
#define USB0_ENDPTSTAT_ETBR_SHIFT (16)
|
|
#define USB0_ENDPTSTAT_ETBR_MASK (0x3f << USB0_ENDPTSTAT_ETBR_SHIFT)
|
|
#define USB0_ENDPTSTAT_ETBR(x) ((x) << USB0_ENDPTSTAT_ETBR_SHIFT)
|
|
|
|
/* --- USB0_ENDPTCOMPLETE values -------------------------------- */
|
|
|
|
/* ERCE: Endpoint receive complete event for physical OUT endpoints 5 to 0 */
|
|
#define USB0_ENDPTCOMPLETE_ERCE_SHIFT (0)
|
|
#define USB0_ENDPTCOMPLETE_ERCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ERCE_SHIFT)
|
|
#define USB0_ENDPTCOMPLETE_ERCE(x) ((x) << USB0_ENDPTCOMPLETE_ERCE_SHIFT)
|
|
|
|
/* ETCE: Endpoint transmit complete event for physical IN endpoints 5 to 0 */
|
|
#define USB0_ENDPTCOMPLETE_ETCE_SHIFT (16)
|
|
#define USB0_ENDPTCOMPLETE_ETCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ETCE_SHIFT)
|
|
#define USB0_ENDPTCOMPLETE_ETCE(x) ((x) << USB0_ENDPTCOMPLETE_ETCE_SHIFT)
|
|
|
|
/* --- USB0_ENDPTCTRL0 values ----------------------------------- */
|
|
|
|
/* RXS: Rx endpoint stall */
|
|
#define USB0_ENDPTCTRL0_RXS_SHIFT (0)
|
|
#define USB0_ENDPTCTRL0_RXS (1 << USB0_ENDPTCTRL0_RXS_SHIFT)
|
|
|
|
/* RXT1_0: Endpoint type */
|
|
#define USB0_ENDPTCTRL0_RXT1_0_SHIFT (2)
|
|
#define USB0_ENDPTCTRL0_RXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_RXT1_0_SHIFT)
|
|
#define USB0_ENDPTCTRL0_RXT1_0(x) ((x) << USB0_ENDPTCTRL0_RXT1_0_SHIFT)
|
|
|
|
/* RXE: Rx endpoint enable */
|
|
#define USB0_ENDPTCTRL0_RXE_SHIFT (7)
|
|
#define USB0_ENDPTCTRL0_RXE (1 << USB0_ENDPTCTRL0_RXE_SHIFT)
|
|
|
|
/* TXS: Tx endpoint stall */
|
|
#define USB0_ENDPTCTRL0_TXS_SHIFT (16)
|
|
#define USB0_ENDPTCTRL0_TXS (1 << USB0_ENDPTCTRL0_TXS_SHIFT)
|
|
|
|
/* TXT1_0: Endpoint type */
|
|
#define USB0_ENDPTCTRL0_TXT1_0_SHIFT (18)
|
|
#define USB0_ENDPTCTRL0_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_TXT1_0_SHIFT)
|
|
#define USB0_ENDPTCTRL0_TXT1_0(x) ((x) << USB0_ENDPTCTRL0_TXT1_0_SHIFT)
|
|
|
|
/* TXE: Tx endpoint enable */
|
|
#define USB0_ENDPTCTRL0_TXE_SHIFT (23)
|
|
#define USB0_ENDPTCTRL0_TXE (1 << USB0_ENDPTCTRL0_TXE_SHIFT)
|
|
|
|
/* --- USB0_ENDPTCTRL1 values ----------------------------------- */
|
|
|
|
/* RXS: Rx endpoint stall */
|
|
#define USB0_ENDPTCTRL1_RXS_SHIFT (0)
|
|
#define USB0_ENDPTCTRL1_RXS (1 << USB0_ENDPTCTRL1_RXS_SHIFT)
|
|
|
|
/* RXT: Endpoint type */
|
|
#define USB0_ENDPTCTRL1_RXT_SHIFT (2)
|
|
#define USB0_ENDPTCTRL1_RXT_MASK (0x3 << USB0_ENDPTCTRL1_RXT_SHIFT)
|
|
#define USB0_ENDPTCTRL1_RXT(x) ((x) << USB0_ENDPTCTRL1_RXT_SHIFT)
|
|
|
|
/* RXI: Rx data toggle inhibit */
|
|
#define USB0_ENDPTCTRL1_RXI_SHIFT (5)
|
|
#define USB0_ENDPTCTRL1_RXI (1 << USB0_ENDPTCTRL1_RXI_SHIFT)
|
|
|
|
/* RXR: Rx data toggle reset */
|
|
#define USB0_ENDPTCTRL1_RXR_SHIFT (6)
|
|
#define USB0_ENDPTCTRL1_RXR (1 << USB0_ENDPTCTRL1_RXR_SHIFT)
|
|
|
|
/* RXE: Rx endpoint enable */
|
|
#define USB0_ENDPTCTRL1_RXE_SHIFT (7)
|
|
#define USB0_ENDPTCTRL1_RXE (1 << USB0_ENDPTCTRL1_RXE_SHIFT)
|
|
|
|
/* TXS: Tx endpoint stall */
|
|
#define USB0_ENDPTCTRL1_TXS_SHIFT (16)
|
|
#define USB0_ENDPTCTRL1_TXS (1 << USB0_ENDPTCTRL1_TXS_SHIFT)
|
|
|
|
/* TXT1_0: Tx Endpoint type */
|
|
#define USB0_ENDPTCTRL1_TXT1_0_SHIFT (18)
|
|
#define USB0_ENDPTCTRL1_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL1_TXT1_0_SHIFT)
|
|
#define USB0_ENDPTCTRL1_TXT1_0(x) ((x) << USB0_ENDPTCTRL1_TXT1_0_SHIFT)
|
|
|
|
/* TXI: Tx data toggle inhibit */
|
|
#define USB0_ENDPTCTRL1_TXI_SHIFT (21)
|
|
#define USB0_ENDPTCTRL1_TXI (1 << USB0_ENDPTCTRL1_TXI_SHIFT)
|
|
|
|
/* TXR: Tx data toggle reset */
|
|
#define USB0_ENDPTCTRL1_TXR_SHIFT (22)
|
|
#define USB0_ENDPTCTRL1_TXR (1 << USB0_ENDPTCTRL1_TXR_SHIFT)
|
|
|
|
/* TXE: Tx endpoint enable */
|
|
#define USB0_ENDPTCTRL1_TXE_SHIFT (23)
|
|
#define USB0_ENDPTCTRL1_TXE (1 << USB0_ENDPTCTRL1_TXE_SHIFT)
|
|
|
|
/* --- USB0_ENDPTCTRL2 values ----------------------------------- */
|
|
|
|
/* RXS: Rx endpoint stall */
|
|
#define USB0_ENDPTCTRL2_RXS_SHIFT (0)
|
|
#define USB0_ENDPTCTRL2_RXS (1 << USB0_ENDPTCTRL2_RXS_SHIFT)
|
|
|
|
/* RXT: Endpoint type */
|
|
#define USB0_ENDPTCTRL2_RXT_SHIFT (2)
|
|
#define USB0_ENDPTCTRL2_RXT_MASK (0x3 << USB0_ENDPTCTRL2_RXT_SHIFT)
|
|
#define USB0_ENDPTCTRL2_RXT(x) ((x) << USB0_ENDPTCTRL2_RXT_SHIFT)
|
|
|
|
/* RXI: Rx data toggle inhibit */
|
|
#define USB0_ENDPTCTRL2_RXI_SHIFT (5)
|
|
#define USB0_ENDPTCTRL2_RXI (1 << USB0_ENDPTCTRL2_RXI_SHIFT)
|
|
|
|
/* RXR: Rx data toggle reset */
|
|
#define USB0_ENDPTCTRL2_RXR_SHIFT (6)
|
|
#define USB0_ENDPTCTRL2_RXR (1 << USB0_ENDPTCTRL2_RXR_SHIFT)
|
|
|
|
/* RXE: Rx endpoint enable */
|
|
#define USB0_ENDPTCTRL2_RXE_SHIFT (7)
|
|
#define USB0_ENDPTCTRL2_RXE (1 << USB0_ENDPTCTRL2_RXE_SHIFT)
|
|
|
|
/* TXS: Tx endpoint stall */
|
|
#define USB0_ENDPTCTRL2_TXS_SHIFT (16)
|
|
#define USB0_ENDPTCTRL2_TXS (1 << USB0_ENDPTCTRL2_TXS_SHIFT)
|
|
|
|
/* TXT1_0: Tx Endpoint type */
|
|
#define USB0_ENDPTCTRL2_TXT1_0_SHIFT (18)
|
|
#define USB0_ENDPTCTRL2_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL2_TXT1_0_SHIFT)
|
|
#define USB0_ENDPTCTRL2_TXT1_0(x) ((x) << USB0_ENDPTCTRL2_TXT1_0_SHIFT)
|
|
|
|
/* TXI: Tx data toggle inhibit */
|
|
#define USB0_ENDPTCTRL2_TXI_SHIFT (21)
|
|
#define USB0_ENDPTCTRL2_TXI (1 << USB0_ENDPTCTRL2_TXI_SHIFT)
|
|
|
|
/* TXR: Tx data toggle reset */
|
|
#define USB0_ENDPTCTRL2_TXR_SHIFT (22)
|
|
#define USB0_ENDPTCTRL2_TXR (1 << USB0_ENDPTCTRL2_TXR_SHIFT)
|
|
|
|
/* TXE: Tx endpoint enable */
|
|
#define USB0_ENDPTCTRL2_TXE_SHIFT (23)
|
|
#define USB0_ENDPTCTRL2_TXE (1 << USB0_ENDPTCTRL2_TXE_SHIFT)
|
|
|
|
/* --- USB0_ENDPTCTRL3 values ----------------------------------- */
|
|
|
|
/* RXS: Rx endpoint stall */
|
|
#define USB0_ENDPTCTRL3_RXS_SHIFT (0)
|
|
#define USB0_ENDPTCTRL3_RXS (1 << USB0_ENDPTCTRL3_RXS_SHIFT)
|
|
|
|
/* RXT: Endpoint type */
|
|
#define USB0_ENDPTCTRL3_RXT_SHIFT (2)
|
|
#define USB0_ENDPTCTRL3_RXT_MASK (0x3 << USB0_ENDPTCTRL3_RXT_SHIFT)
|
|
#define USB0_ENDPTCTRL3_RXT(x) ((x) << USB0_ENDPTCTRL3_RXT_SHIFT)
|
|
|
|
/* RXI: Rx data toggle inhibit */
|
|
#define USB0_ENDPTCTRL3_RXI_SHIFT (5)
|
|
#define USB0_ENDPTCTRL3_RXI (1 << USB0_ENDPTCTRL3_RXI_SHIFT)
|
|
|
|
/* RXR: Rx data toggle reset */
|
|
#define USB0_ENDPTCTRL3_RXR_SHIFT (6)
|
|
#define USB0_ENDPTCTRL3_RXR (1 << USB0_ENDPTCTRL3_RXR_SHIFT)
|
|
|
|
/* RXE: Rx endpoint enable */
|
|
#define USB0_ENDPTCTRL3_RXE_SHIFT (7)
|
|
#define USB0_ENDPTCTRL3_RXE (1 << USB0_ENDPTCTRL3_RXE_SHIFT)
|
|
|
|
/* TXS: Tx endpoint stall */
|
|
#define USB0_ENDPTCTRL3_TXS_SHIFT (16)
|
|
#define USB0_ENDPTCTRL3_TXS (1 << USB0_ENDPTCTRL3_TXS_SHIFT)
|
|
|
|
/* TXT1_0: Tx Endpoint type */
|
|
#define USB0_ENDPTCTRL3_TXT1_0_SHIFT (18)
|
|
#define USB0_ENDPTCTRL3_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL3_TXT1_0_SHIFT)
|
|
#define USB0_ENDPTCTRL3_TXT1_0(x) ((x) << USB0_ENDPTCTRL3_TXT1_0_SHIFT)
|
|
|
|
/* TXI: Tx data toggle inhibit */
|
|
#define USB0_ENDPTCTRL3_TXI_SHIFT (21)
|
|
#define USB0_ENDPTCTRL3_TXI (1 << USB0_ENDPTCTRL3_TXI_SHIFT)
|
|
|
|
/* TXR: Tx data toggle reset */
|
|
#define USB0_ENDPTCTRL3_TXR_SHIFT (22)
|
|
#define USB0_ENDPTCTRL3_TXR (1 << USB0_ENDPTCTRL3_TXR_SHIFT)
|
|
|
|
/* TXE: Tx endpoint enable */
|
|
#define USB0_ENDPTCTRL3_TXE_SHIFT (23)
|
|
#define USB0_ENDPTCTRL3_TXE (1 << USB0_ENDPTCTRL3_TXE_SHIFT)
|
|
|
|
/* --- USB0_ENDPTCTRL4 values ----------------------------------- */
|
|
|
|
/* RXS: Rx endpoint stall */
|
|
#define USB0_ENDPTCTRL4_RXS_SHIFT (0)
|
|
#define USB0_ENDPTCTRL4_RXS (1 << USB0_ENDPTCTRL4_RXS_SHIFT)
|
|
|
|
/* RXT: Endpoint type */
|
|
#define USB0_ENDPTCTRL4_RXT_SHIFT (2)
|
|
#define USB0_ENDPTCTRL4_RXT_MASK (0x3 << USB0_ENDPTCTRL4_RXT_SHIFT)
|
|
#define USB0_ENDPTCTRL4_RXT(x) ((x) << USB0_ENDPTCTRL4_RXT_SHIFT)
|
|
|
|
/* RXI: Rx data toggle inhibit */
|
|
#define USB0_ENDPTCTRL4_RXI_SHIFT (5)
|
|
#define USB0_ENDPTCTRL4_RXI (1 << USB0_ENDPTCTRL4_RXI_SHIFT)
|
|
|
|
/* RXR: Rx data toggle reset */
|
|
#define USB0_ENDPTCTRL4_RXR_SHIFT (6)
|
|
#define USB0_ENDPTCTRL4_RXR (1 << USB0_ENDPTCTRL4_RXR_SHIFT)
|
|
|
|
/* RXE: Rx endpoint enable */
|
|
#define USB0_ENDPTCTRL4_RXE_SHIFT (7)
|
|
#define USB0_ENDPTCTRL4_RXE (1 << USB0_ENDPTCTRL4_RXE_SHIFT)
|
|
|
|
/* TXS: Tx endpoint stall */
|
|
#define USB0_ENDPTCTRL4_TXS_SHIFT (16)
|
|
#define USB0_ENDPTCTRL4_TXS (1 << USB0_ENDPTCTRL4_TXS_SHIFT)
|
|
|
|
/* TXT1_0: Tx Endpoint type */
|
|
#define USB0_ENDPTCTRL4_TXT1_0_SHIFT (18)
|
|
#define USB0_ENDPTCTRL4_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL4_TXT1_0_SHIFT)
|
|
#define USB0_ENDPTCTRL4_TXT1_0(x) ((x) << USB0_ENDPTCTRL4_TXT1_0_SHIFT)
|
|
|
|
/* TXI: Tx data toggle inhibit */
|
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#define USB0_ENDPTCTRL4_TXI_SHIFT (21)
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#define USB0_ENDPTCTRL4_TXI (1 << USB0_ENDPTCTRL4_TXI_SHIFT)
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/* TXR: Tx data toggle reset */
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#define USB0_ENDPTCTRL4_TXR_SHIFT (22)
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#define USB0_ENDPTCTRL4_TXR (1 << USB0_ENDPTCTRL4_TXR_SHIFT)
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/* TXE: Tx endpoint enable */
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#define USB0_ENDPTCTRL4_TXE_SHIFT (23)
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#define USB0_ENDPTCTRL4_TXE (1 << USB0_ENDPTCTRL4_TXE_SHIFT)
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/* --- USB0_ENDPTCTRL5 values ----------------------------------- */
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/* RXS: Rx endpoint stall */
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#define USB0_ENDPTCTRL5_RXS_SHIFT (0)
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#define USB0_ENDPTCTRL5_RXS (1 << USB0_ENDPTCTRL5_RXS_SHIFT)
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/* RXT: Endpoint type */
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#define USB0_ENDPTCTRL5_RXT_SHIFT (2)
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#define USB0_ENDPTCTRL5_RXT_MASK (0x3 << USB0_ENDPTCTRL5_RXT_SHIFT)
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#define USB0_ENDPTCTRL5_RXT(x) ((x) << USB0_ENDPTCTRL5_RXT_SHIFT)
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/* RXI: Rx data toggle inhibit */
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#define USB0_ENDPTCTRL5_RXI_SHIFT (5)
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#define USB0_ENDPTCTRL5_RXI (1 << USB0_ENDPTCTRL5_RXI_SHIFT)
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/* RXR: Rx data toggle reset */
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#define USB0_ENDPTCTRL5_RXR_SHIFT (6)
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#define USB0_ENDPTCTRL5_RXR (1 << USB0_ENDPTCTRL5_RXR_SHIFT)
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/* RXE: Rx endpoint enable */
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#define USB0_ENDPTCTRL5_RXE_SHIFT (7)
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#define USB0_ENDPTCTRL5_RXE (1 << USB0_ENDPTCTRL5_RXE_SHIFT)
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/* TXS: Tx endpoint stall */
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#define USB0_ENDPTCTRL5_TXS_SHIFT (16)
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#define USB0_ENDPTCTRL5_TXS (1 << USB0_ENDPTCTRL5_TXS_SHIFT)
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/* TXT1_0: Tx Endpoint type */
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#define USB0_ENDPTCTRL5_TXT1_0_SHIFT (18)
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#define USB0_ENDPTCTRL5_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL5_TXT1_0_SHIFT)
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#define USB0_ENDPTCTRL5_TXT1_0(x) ((x) << USB0_ENDPTCTRL5_TXT1_0_SHIFT)
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/* TXI: Tx data toggle inhibit */
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#define USB0_ENDPTCTRL5_TXI_SHIFT (21)
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#define USB0_ENDPTCTRL5_TXI (1 << USB0_ENDPTCTRL5_TXI_SHIFT)
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/* TXR: Tx data toggle reset */
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#define USB0_ENDPTCTRL5_TXR_SHIFT (22)
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#define USB0_ENDPTCTRL5_TXR (1 << USB0_ENDPTCTRL5_TXR_SHIFT)
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/* TXE: Tx endpoint enable */
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#define USB0_ENDPTCTRL5_TXE_SHIFT (23)
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#define USB0_ENDPTCTRL5_TXE (1 << USB0_ENDPTCTRL5_TXE_SHIFT)
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/* --- USB1 registers ------------------------------------------------------ */
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/* TODO */
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#endif
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