169 lines
4.9 KiB
C
169 lines
4.9 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
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* Copyright (C) 2014 Felix Held <felix-libopencm3@felixheld.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PIO.H
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The order of header inclusion is important. pio.h includes the device
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specific memorymap.h header before including this header file.*/
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#if defined(LIBOPENCM3_PIO_H)
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#ifndef LIBOPENCM3_PIO_COMMON_ALL_H
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#define LIBOPENCM3_PIO_COMMON_ALL_H
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#include <libopencm3/cm3/common.h>
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/* --- Convenience macros ------------------------------------------------ */
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/* GPIO port base addresses (for convenience) */
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#define PIOA PIOA_BASE
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#define PIOB PIOB_BASE
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#define PIOC PIOC_BASE
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#define PIOD PIOD_BASE
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#define PIOE PIOE_BASE
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#define PIOF PIOF_BASE
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#define PIOG PIOG_BASE
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#define PIOH PIOH_BASE
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/* --- PIO registers ----------------------------------------------------- */
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/* PIO Enable Register */
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#define PIO_PER(port) MMIO32((port) + 0x0000)
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/* PIO Disable Register */
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#define PIO_PDR(port) MMIO32((port) + 0x0004)
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/* PIO Status Register */
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#define PIO_PSR(port) MMIO32((port) + 0x0008)
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/* Output Enable Register */
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#define PIO_OER(port) MMIO32((port) + 0x0010)
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/* Output Disable Register */
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#define PIO_ODR(port) MMIO32((port) + 0x0014)
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/* Output Status Register */
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#define PIO_OSR(port) MMIO32((port) + 0x0018)
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/* Glitch Input Filter Enable Register */
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#define PIO_IFER(port) MMIO32((port) + 0x0020)
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/* Glitch Input Filter Disable Register */
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#define PIO_IFDR(port) MMIO32((port) + 0x0024)
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/* Glitch Input Filter Status Register */
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#define PIO_IFSR(port) MMIO32((port) + 0x0028)
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/* Set Output Data Register */
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#define PIO_SODR(port) MMIO32((port) + 0x0030)
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/* Clear Output Data Register */
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#define PIO_CODR(port) MMIO32((port) + 0x0034)
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/* Output Data Status Register */
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#define PIO_ODSR(port) MMIO32((port) + 0x0038)
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/* Pin Data Status Register */
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#define PIO_PDSR(port) MMIO32((port) + 0x003C)
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/* Interrupt Enable Register */
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#define PIO_IER(port) MMIO32((port) + 0x0040)
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/* Interrupt Disable Register */
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#define PIO_IDR(port) MMIO32((port) + 0x0044)
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/* Interrupt Mask Register */
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#define PIO_IMR(port) MMIO32((port) + 0x0048)
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/* Interrupt Status Register */
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#define PIO_ISR(port) MMIO32((port) + 0x004C)
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/* Multi-driver Enable Register */
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#define PIO_MDER(port) MMIO32((port) + 0x0050)
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/* Multi-driver Disable Register */
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#define PIO_MDDR(port) MMIO32((port) + 0x0054)
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/* Multi-driver Status Register */
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#define PIO_MDSR(port) MMIO32((port) + 0x0058)
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/* Pull-up Disable Register */
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#define PIO_PUDR(port) MMIO32((port) + 0x0060)
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/* Pull-up Enable Register */
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#define PIO_PUER(port) MMIO32((port) + 0x0064)
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/* Pad Pull-up Status Register */
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#define PIO_PUSR(port) MMIO32((port) + 0x0068)
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/* Slow Clock Divider Debouncing Register */
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#define PIO_SCDR(port) MMIO32((port) + 0x008C)
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/* Output Write Enable */
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#define PIO_OWER(port) MMIO32((port) + 0x00A0)
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/* Output Write Disable */
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#define PIO_OWDR(port) MMIO32((port) + 0x00A4)
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/* Output Write Status Register */
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#define PIO_OWSR(port) MMIO32((port) + 0x00A8)
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/* Additional Interrupt Modes Enable Register */
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#define PIO_AIMER(port) MMIO32((port) + 0x00B0)
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/* Additional Interrupt Modes Disables Register */
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#define PIO_AIMDR(port) MMIO32((port) + 0x00B4)
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/* Additional Interrupt Modes Mask Register */
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#define PIO_AIMMR(port) MMIO32((port) + 0x00B8)
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/* Edge Select Register */
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#define PIO_ESR(port) MMIO32((port) + 0x00C0)
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/* Level Select Register */
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#define PIO_LSR(port) MMIO32((port) + 0x00C4)
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/* Edge/Level Status Register */
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#define PIO_ELSR(port) MMIO32((port) + 0x00C8)
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/* Falling Edge/Low Level Select Register */
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#define PIO_FELLSR(port) MMIO32((port) + 0x00D0)
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/* Rising Edge/High Level Select Register */
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#define PIO_REHLSR(port) MMIO32((port) + 0x00D4)
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/* Fall/Rise - Low/High Status Register */
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#define PIO_FRLHSR(port) MMIO32((port) + 0x00D8)
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/* Lock Status */
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#define PIO_LOCKSR(port) MMIO32((port) + 0x00E0)
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/* Write Protect Mode Register */
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#define PIO_WPMR(port) MMIO32((port) + 0x00E4)
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/* Write Protect Status Register */
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#define PIO_WPSR(port) MMIO32((port) + 0x00E8)
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#endif
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#else
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#warning "pio_common_all.h should not be included explicitly, only via pio.h"
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#endif
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