2ca56f4c21
PLL configuration on the H7 is pretty involved, and takes a number of configurations to make it work. In order to make peripheral drivers a bit easier to implement, working with a soft clock tree in the rcc module which stores the clock settings for each clock as they are setup such that users can request the clock value from the RCC module for configuration. Added getter for the clock which allows the user to pass the base address of the peripheral, and get the peripheral clock value for convenience. Clock configuration is still missing values for setting up all of the kernel clocks for the peripherals, but this is in work, and there is a framework to do so. Have tested to 400MHz without issue. Peripherals that are explicitly supported are working and the clock tree values appear to follow correctly. Added LDO settings to allow setting the scaling to support high frequencies.
135 lines
4.0 KiB
C
135 lines
4.0 KiB
C
/** @defgroup pwr_defines PWR Defines
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@brief <b>Defined Constants and Types for the STM32H7xx Power Control</b>
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@ingroup STM32H7xx_defines
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@version 1.0.0
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Brian Viele <vielster@allocor.tech>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PWR_H
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#define LIBOPENCM3_PWR_H
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/**@{*/
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/** @defgroup pwr_registers PWR Registers
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@{*/
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/** Power control register. */
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#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00)
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/** Power control/status register. */
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#define PWR_CSR1 MMIO32(POWER_CONTROL_BASE + 0x04)
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/** Power control register 2. */
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#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x08)
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/** Power control register 3. */
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#define PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x0C)
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/** CPU Power control register 3. */
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#define PWR_CPUCR MMIO32(POWER_CONTROL_BASE + 0x10)
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/** D3 Domain Power Control register. */
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#define PWR_D3CR MMIO32(POWER_CONTROL_BASE + 0x18)
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/** Wakeup Domain Power Control register. */
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#define PWR_WKUPCR MMIO32(POWER_CONTROL_BASE + 0x20)
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/*@}*/
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/** VOS[15:14]: Regulator voltage scaling output selection */
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#define PWR_CR1_SVOS_SHIFT 14
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#define PWR_CR1_SVOS_SCALE_3 (0x3)
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#define PWR_CR1_SVOS_SCALE_4 (0x2)
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#define PWR_CR1_SVOS_SCALE_5 (0x1)
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#define PWR_CR1_SVOS_MASK (0x3)
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/** DBP[8]: Disable backup domain write protection. */
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#define PWR_CR1_DBP (1 << 8)
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/** CSR1 Register Bits */
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#define PWR_CSR1_AVDO BIT16
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#define PWR_CSR1_ACTVOS_SHIFT 14
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#define PWR_CSR1_ACTVOSRDY BIT13
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#define PWR_CSR1_PVDO BIT4
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/** CR3 Register Bits */
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#define PWR_CR3_USB33RDY BIT26
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#define PWR_CR3_USBREGEN BIT25
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#define PWR_CR3_USB33DEN BIT24
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#define PWR_CR3_VBRS BIT9
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#define PWR_CR3_VBE BIT8
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#define PWR_CR3_SCUEN BIT2
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#define PWR_CR3_LDOEN BIT1
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#define PWR_CR3_BYPASS BIT0
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/** D3CR Register Bits */
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#define PWR_D3CR_VOS_SHIFT 14
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#define PWR_D3CR_VOSRDY BIT13
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#define PWR_D3CR_VOS_SCALE_3 (0x3)
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#define PWR_D3CR_VOS_SCALE_2 (0x2)
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#define PWR_D3CR_VOS_SCALE_1 (0x1)
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#define PWR_D3CR_VOS_MASK (0x03)
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/* --- Function prototypes ------------------------------------------------- */
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enum pwr_svos_scale {
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PWR_SVOS_SCALE3 = PWR_CR1_SVOS_SCALE_3 << PWR_CR1_SVOS_SHIFT,
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PWR_SVOS_SCALE4 = PWR_CR1_SVOS_SCALE_4 << PWR_CR1_SVOS_SHIFT,
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PWR_SVOS_SCALE5 = PWR_CR1_SVOS_SCALE_5 << PWR_CR1_SVOS_SHIFT,
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};
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enum pwr_vos_scale {
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PWR_VOS_SCALE_0 = 0, /* Note: This state requires SYSCFG ODEN set. */
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PWR_VOS_SCALE_1 = (PWR_D3CR_VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT),
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PWR_VOS_SCALE_2 = (PWR_D3CR_VOS_SCALE_2 << PWR_D3CR_VOS_SHIFT),
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PWR_VOS_SCALE_3 = (PWR_D3CR_VOS_SCALE_3 << PWR_D3CR_VOS_SHIFT)
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};
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BEGIN_DECLS
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/** @defgroup pwr_peripheral_api PWR Peripheral API
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* @ingroup peripheral_apis
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@{*/
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/** Set power subsystem to utilize the LDO for CPU. */
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void pwr_set_mode_ldo(void);
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/** Set the voltage scaling/strength for the internal LDO when in Stop mode.
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* @param[in] scale Voltage scale value to set.
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*/
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void pwr_set_svos_scale(enum pwr_svos_scale scale);
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/** Set the voltage scaling/strength for the internal LDO while running.
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* @param[in] scale Voltage scale value to set.
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*/
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void pwr_set_vos_scale(enum pwr_vos_scale scale);
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END_DECLS
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/**@}*/
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#endif
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