1ad2cda496
Just get them all included as they are. Gets them grouped up and visible so we can start clarifying the rest of their docs.
94 lines
2.6 KiB
C
94 lines
2.6 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CM3_FPB_H
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#define LIBOPENCM3_CM3_FPB_H
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/**
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* @defgroup cm_fpb Cortex-M Flash Patch and Breakpoint (FPB) unit
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* @ingroup CM3_defines
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* @{
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*/
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/* Those defined only on ARMv7 and above */
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#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
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#error "Flash Patch and Breakpoint not available in CM0"
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#endif
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/* Note: We always use "FPB" as abbreviation, docs sometimes use only "FP". */
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/* --- FPB registers ------------------------------------------------------- */
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/* Flash Patch Control (FPB_CTRL) */
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#define FPB_CTRL MMIO32(FPB_BASE + 0)
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/* Flash Patch Remap (FPB_REMAP) */
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#define FPB_REMAP MMIO32(FPB_BASE + 4)
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/* Flash Patch Comparator (FPB_COMPx) */
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#define FPB_COMP (&MMIO32(FPB_BASE + 8))
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/* CoreSight Lock Status Register for this peripheral */
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#define FPB_LSR MMIO32(FPB_BASE + 0xFB4)
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/* CoreSight Lock Access Register for this peripheral */
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#define FPB_LAR MMIO32(FPB_BASE + 0xFB0)
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/* TODO: PID, CID */
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/* --- FPB_CTRL values ----------------------------------------------------- */
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/* Bits [31:15]: Reserved, read as zero, writes ignored */
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#define FPB_CTRL_NUM_CODE2_MASK (0x7 << 12)
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#define FPB_CTRL_NUM_LIT_MASK (0xf << 8)
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#define FPB_CTRL_NUM_CODE1_MASK (0xf << 4)
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/* Bits [3:2]: Reserved */
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#define FPB_CTRL_KEY (1 << 1)
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#define FPB_CTRL_ENABLE (1 << 0)
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/* --- FPB_REMAP values ---------------------------------------------------- */
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/* TODO */
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/* --- FPB_COMPx values ---------------------------------------------------- */
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#define FPB_COMP_REPLACE_REMAP (0x0 << 30)
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#define FPB_COMP_REPLACE_BREAK_LOWER (0x1 << 30)
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#define FPB_COMP_REPLACE_BREAK_UPPER (0x2 << 30)
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#define FPB_COMP_REPLACE_BREAK_BOTH (0x3 << 30)
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#define FPB_COMP_REPLACE_MASK (0x3 << 30)
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/* Bit 29: Reserved */
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/* TODO */
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/* Bit 1: Reserved */
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#define FPB_COMP_ENABLE (1 << 0)
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/**@}*/
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#endif
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