330d5fd5be
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by GigaDevice, which features pin-to-pin package compatibility with STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds CAN support. Currently the code mainly targets GD32F130 and F150 chips. Some register are different between F130/150 and F170/190, just like the difference between STM32F1 Performance line and Connectivity line. From the perspective of registers and memory map, GD32F1X0 seems like a mixture between STM32F1 and STM32F0 (because it is designed to be pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of code are shared between STM32 and GD32, and these code are specially processed to include the GD32 headers instead of STM32 headers when meet GD32F1X0. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Karl Palsson <karlp@tweak.net.au> gd32/rcc.[ch] are forks of stm32f1/rcc gd32/flash.[ch] are forks of stm32f0/flash No attempts at deduplicating this have been done at this stage. We can see where they move in the future.
60 lines
1.0 KiB
JSON
60 lines
1.0 KiB
JSON
{
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"irqs": [
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"wwdg",
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"pvd",
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"rtc",
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"flash",
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"rcc",
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"exti0_1",
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"exti2_3",
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"exti4_15",
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"tsc",
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"dma_channel1",
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"dma_channel2_3",
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"dma_channel4_5",
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"adc_comp",
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"tim1_brk_up_trg_com",
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"tim1_cc",
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"tim2",
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"tim3",
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"tim6_dac",
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"reserved0",
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"tim14",
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"tim15",
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"tim16",
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"tim17",
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"i2c1_ev",
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"i2c2_ev",
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"spi1",
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"spi2",
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"usart1",
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"usart2",
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"reserved1",
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"cec_can",
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"reserved2",
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"i2c1_er",
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"reserved3",
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"i2c2_er",
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"i2c3_ev",
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"i2c3_er",
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"usb_lp",
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"usb_hp",
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"reserved4",
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"reserved5",
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"reserved6",
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"usb_wakeup",
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"reserved7",
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"reserved8",
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"reserved9",
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"reserved10",
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"reserved11",
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"dma_channel6_7",
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"reserved12",
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"reserved13",
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"spi3"
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],
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"partname_humanreadable": "GD32F1x0 Series",
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"partname_doxygen": "GD32F1x0",
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"includeguard": "LIBOPENCM3_GD32F1X0_NVIC_H"
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}
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