330d5fd5be
GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by GigaDevice, which features pin-to-pin package compatibility with STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds CAN support. Currently the code mainly targets GD32F130 and F150 chips. Some register are different between F130/150 and F170/190, just like the difference between STM32F1 Performance line and Connectivity line. From the perspective of registers and memory map, GD32F1X0 seems like a mixture between STM32F1 and STM32F0 (because it is designed to be pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of code are shared between STM32 and GD32, and these code are specially processed to include the GD32 headers instead of STM32 headers when meet GD32F1X0. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Karl Palsson <karlp@tweak.net.au> gd32/rcc.[ch] are forks of stm32f1/rcc gd32/flash.[ch] are forks of stm32f0/flash No attempts at deduplicating this have been done at this stage. We can see where they move in the future.
64 lines
2.0 KiB
C
64 lines
2.0 KiB
C
#if defined(STM32F0)
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# include <libopencmsis/stm32/f0/irqhandlers.h>
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#elif defined(STM32F1)
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# include <libopencmsis/stm32/f1/irqhandlers.h>
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#elif defined(STM32F2)
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# include <libopencmsis/stm32/f2/irqhandlers.h>
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#elif defined(STM32F3)
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# include <libopencmsis/stm32/f3/irqhandlers.h>
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#elif defined(STM32F4)
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# include <libopencmsis/stm32/f4/irqhandlers.h>
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#elif defined(STM32F7)
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# include <libopencmsis/stm32/f7/irqhandlers.h>
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#elif defined(STM32L0)
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# include <libopencmsis/stm32/l0/irqhandlers.h>
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#elif defined(STM32L1)
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# include <libopencmsis/stm32/l1/irqhandlers.h>
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#elif defined(STM32L4)
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# include <libopencmsis/stm32/l4/irqhandlers.h>
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#elif defined(GD32F1X0)
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# include <libopencmsis/gd32/f1x0/irqhandlers.h>
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#elif defined(EFM32TG)
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# include <libopencmsis/efm32/efm32tg/irqhandlers.h>
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#elif defined(EFM32G)
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# include <libopencmsis/efm32/efm32g/irqhandlers.h>
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#elif defined(EFM32HG)
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# include <libopencmsis/efm32/efm32hg/irqhandlers.h>
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#elif defined(EFM32LG)
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# include <libopencmsis/efm32/efm32lg/irqhandlers.h>
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#elif defined(EFM32GG)
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# include <libopencmsis/efm32/efm32gg/irqhandlers.h>
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#elif defined(LPC13XX)
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# include <libopencmsis/lpc13xx/irqhandlers.h>
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#elif defined(LPC17XX)
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# include <libopencmsis/lpc17xx/irqhandlers.h>
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#elif defined(LPC43XX_M4)
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# include <libopencmsis/lpc43xx/m4/irqhandlers.h>
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#elif defined(LPC43XX_M0)
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# include <libopencmsis/lpc43xx/m0/irqhandlers.h>
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#elif defined(SAM3A)
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# include <libopencmsis/sam/3a/irqhandlers.h>
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#elif defined(SAM3N)
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# include <libopencmsis/sam/3n/irqhandlers.h>
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#elif defined(SAM3S)
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# include <libopencmsis/sam/3s/irqhandlers.h>
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#elif defined(SAM3U)
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# include <libopencmsis/sam/3u/irqhandlers.h>
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#elif defined(SAM3X)
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# include <libopencmsis/sam/3x/irqhandlers.h>
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#elif defined(SAMD)
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# include <libopencmsis/sam/d/irqhandlers.h>
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#elif defined(LM3S) || defined(LM4F)
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/* Yes, we use the same interrupt table for both LM3S and LM4F */
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# include <libopencmsis/lm3s/irqhandlers.h>
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#else
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# warning"no chipset defined; user interrupts are not redirected"
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#endif
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